External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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5.3.2. Generating the EMIF Design Example

  1. Generate an EMIF design example with with the Simulation and Synthesis options selected.
    Figure 99. Generating a Design Example for Simulation and Synthesis
    The following discussion assumes that the design example targets a DDR4 RDIMM x64 interface with data mask enabled, implemented on the Intel® Agilex™ F-Series FPGA Development Kit.
  2. With the .qpf file in the synthesizable design example, you can launch the project and open the ed_sim.qsys file to edit the simulation design example with the Platform Designer.
  3. After generating the simulation design example, delete the ed_sim folder in the simulation design example. You regenerate the ed_sim folder after incorporating the AXI4 Master BFM to the simulation design example.

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