External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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11.7. Debugging with the External Memory Interface Debug Toolkit

The External Memory Interface Debug Toolkit for Intel® Agilex™ FPGAs provides access to data collected by the Nios® II sequencer during memory calibration, as well as analysis tools to evaluate the stability of the calibrated interface and assess hardware conditions.

The toolkit provides the following reports:

  • Interface and memory configuration, such as external memory protocol and interface width.
  • Calibration results including calibration status (pass or fail), calibration failure stage (if applicable), delay settings and margins, as well as VREF settings and margins.

The available task and analysis capabilities include the following:

  • Requesting recalibration of the memory interface.
  • Reading the probe data or writing the source data to the In-System Sources and Probes (ISSPs) instances in the design.
  • Viewing the delay setting on any pin in the selected interface and updating it if necessary.
  • Rerunning the traffic generator in the design example.
  • Running VREF Margining on the interface.
  • Running Driver Margining on the interface.
  • Calibrating or updating the termination settings (or both).

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