External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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11.10.4. Debug Interface Structure

The topics in this section outline the structure of the debug interface.

These structures are populated during calibration and can be accessed afterwards to see the results of the calibration. If you change values in these structures the values in hardware do not change; to change values in hardware, you must change this information in the calibration bus instead. These structures are populated only if you have enabled debugging in this row, in the emif_cal IP.

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