External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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11.6.1.2.8. OCT and ODT Usage

Modern external memory interface designs typically use OCT for the FPGA end of the line, and ODT for the memory component end of the line. If either the OCT or ODT are incorrectly configured or enabled, signal integrity problems occur.

For the FPGA, ensure that you perform the following:

  • Connect the RZQ pin to the correct resistors (either a 240 Ω or 100 Ω resistor, depending on the desired OCT impedance) and pull-down to ground in the schematic or PCB.
  • Contain the RZQ pins within a bank of the device that is operating at the same VCCIO voltage as the interface that is terminated.
  • Review the Fitter Pin-Out file for RZQ pins to ensure that they are on the correct pins, and that only the correct number of calibration blocks exists in your design.
  • Check in the fitter report that the input, output, and bidirectional signals with calibrated OCT all have the termination control block applicable to the associated RZQ pins.

For the memory components, ensure that you perform the following:

  • Connect the required resistor to the correct pin on each and every component, and ensure that it is pulled to the correct voltage.
  • Place the required resistor close to the memory component.
  • Correctly configure the IP to enable the desired termination at initialization time.
  • Check that the speed grade of memory component supports the selected ODT setting.
  • Check that the second source part that may have been fitted to the PCB, supports the same ODT settings as the original.

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