External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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6.5.7. Intel® Agilex™ EMIF Pin Swapping Guidelines

In Intel® Agilex™ devices, EMIF pin swapping is allowed under certain conditions.

An IO12 lane in an EMIF data byte includes 12 signal pins (pins 0,1,2,3,4,5,6,7,8,9,10,11) at the package level. These 12 x I/O pins are arranged into 6 groups of 2 pins each, called pairs (pair 0 for pins 0/1, pair 1 for pins 2/3, pair 2 for pins 4/5, pair 3 for pins 6/7, pair 4 for pins 8/9, and pair 5 for pins 10/11).

DDR4 interface x 8 data lane

The following are EMIF I/O pin swapping restrictions applicable to a DDR4 interface ×8 data lane:

  • One-byte data lane must be assigned for each IO12 lane, where the byte lane covers DQ [0:7], DQSp/DQSn and DBIn.
  • DQSp must go to pin 4 in IO12 pins.
  • DQSn must go to pin 5 in IO12 pins.
  • DBIn must go to pin 6 in IO12 pins. If the interface does not use the DBIn pin, this pin 6 in IO12 lane must remain unconnected.
  • Pin 7 in IO12 lane remains unconnected. Intel® recommends that you connect this pin 7 to the TDQS dummy load of the memory component and route it as a differential trace along with DBIn (pin 6). This facilitates ×4 or ×8 data interoperability in DIMMs configuration.
  • You can connect data byte (DQ [0:7]) to any pins [0,1,2,3,8,9,10,11] in IO12 lane. Any permutation within selected pins is permitted.

DDR4 interface x 4 data lane

Intel® Agilex™ devices allow you to swap data pins within memory interfaces under certain conditions to simplify PCB routing. This table lists the swapping rules for DDR4 x4 and x8 interfaces. (Note that the rules for pin swapping for Intel® Agilex™ devices are stricter than the rules for previous 10-series device families.)

An IO12 lane in an external memory interface consists of 12 signal pins, denoted 0-11. For DDR4 x8 interfaces, two pins are reserved for DQS-P and DQS-N signals, one pin is reserved for the optional DM/DBI signal, one pin must be reserved, and the remaining eight pins are for DQ signals. The following table lists the supported pin functionality and the groups of pins that may be swapped amongst each other. Pins belonging to the same swap group may be freely interchanged with each other.

Table 118.  
Pin Index within IO12 DDR4 x8 Data Lane Function Swap Considerations
0 DQ Pin Swap Group “A”
1 DQ Pin Swap Group “A”
2 DQ Pin Swap Group “A”
3 DQ Pin Swap Group “A”
4 DQS-P Pin Fixed Location (not swappable)
5 DQS-N Pin Fixed Location (not swappable)
6 DM/DBI Pin Fixed Location (not swappable)
7 Unused Fixed Location (not swappable)
8 DQ Pin Swap Group “A”
9 DQ Pin Swap Group “A”
10 DQ Pin Swap Group “A”
11 DQ Pin Swap Group “A”

For DDR4 x4 interfaces, two nibbles must be packed into the same IO12 lane. Four pins are reserved for DQS-P and DQS-N signals and the remaining eight pins are used to implement the DQ signals. The IO12 lane is divided into upper and lower halves to accommodate each nibble. Signals belonging to one nibble cannot be swapped with signals belonging to the other nibble. DQ signals within a nibble swap group may be swapped with each other. Entire nibbles—that is, nibble 0 and nibble 1—may also be swapped with each other provided the DQS pin functionality transfers to the correct pin locations. However, this process is not recommended for JEDEC-compliant DIMM interfaces, as it prohibits the interoperability between DIMMs constructed with x4 components and DIMMs constructed with x8 components as described in x4 DIMM Implementation .

The following table lists the supported pin functionality in x4 mode and the pins that may be swapped with each other.

Table 119.  
Pin Index within IO12 DDR4 x4 Data Lane Function Swap Considerations
0 DQ Pin (lower nibble) Swap Group “A” Nibble 0
1 DQ Pin (lower nibble) Swap Group “A”
2 DQ Pin (lower nibble) Swap Group “A”
3 DQ Pin (lower nibble) Swap Group “A”
4 DQS-P Pin (lower nibble) Fixed Location (not swappable)
5 DQS-N Pin (lower nibble) Fixed Location (not swappable)
6 DQS-P Pin (upper nibble) Fixed Location (not swappable) Nibble 1
7 DQS-N Pin (upper nibble) Fixed Location (not swappable)
8 DQ Pin (upper nibble) Swap Group “B”
9 DQ Pin (upper nibble) Swap Group “B”
10 DQ Pin (upper nibble) Swap Group “B”
11 DQ Pin (upper nibble) Swap Group “B”
  • Nibble 1 must correspond to DQS[17:9] on a physical JEDEC-compliant DIMM for x4/x8 interoperability.
  • Nibbles 0 and 1 must follow the same skew matching rules among all 12 signals in the IO12 lane as are specified for a x8-based DQS group.
Note:
  • Although the current version of the Intel® Quartus® Prime software may not enforce all of the rules listed in the above table, be aware that all of these rules may be enforced in later versions of the software.
  • At present, the Intel® Quartus® Prime software checks the following:
    • Address and command pin placement, per the Intel® Agilex™ External Memory Interface Pin Information file, which is available here: Pin-Out Files for Intel FPGA Devices.
    • For x8, the Intel® Quartus® Prime software checks the following:
      • DQS p/n are on pin index 4 and pin index 5 in an I/O lane.
      • DM/DBI is on pin index 6.
      • DQ[x] are on pin indices [11:8] and [3:0].
    • For x4, the Intel® Quartus® Prime software checks the following:
      • DQS p/n on pin index 4 and pin index 5 and associated DQs are within the corresponding IO12 lane.
      • DQS p/n on pin index 6 and pin index 7 and associated DQs are within the corresponding IO12 lane.
      You are responsible for ensuring that these conditions are met.
  • The Intel® Quartus® Prime software does not currently check whether DQ pins associated with the lower nibble DQS are actually placed in pin[3:0] or whether DQ pins associated with the upper nibble DQS are actually placed in pin[11:8].

DDR4 interface x 4 or x8 A/C and CLK lane

Address and command and control signals in a bank cannot be swapped.

CLKp/n bits (the p and n lanes) and DQS bits cannot be swapped with each other.

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