External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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7.4.4. Intel® Agilex™ EMIF Design Guideline Summary

At a high level, the Intel® Agilex™ device EMIF design guidelines are summarized below.
  1. Define the stackup and topology for the PCB.
  2. Follow the general and specific routing guidelines in this document for target impedance, the maximum trace length on the mother board, and the spacing between traces based on the provided table for EMIF specific topology on the PCB. For EMIF topologies not covered by this document, contact your Intel® support representative.
  3. Follow the skew and length (package plus PCB) guidelines for your specific topology.
  4. Follow the recommended power delivery guidelines for memory components and specific PCB EMIF topology.
  5. For post-layout simulation, follow the guidelines in the I/O Timing Closure chapter.

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