External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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6.5.6. DDR4 Routing Guidelines: Discrete (Component) Topologies

This section discusses two topologies for down-memory configurations: DDR4 single rank × 8 and DDR4 single rank × 16 for a 72 bit interface.

Intel® strongly recommends that you perform simulations using extracted PCB models to ensure that component topologies remain robust under all PCB manufacturing tolerances. Also, carefully consider the number of components on the flyby chain, because every additional component on the flyby chain reduces timing margin on the address/command bus. Take care to provide a proper VTT termination voltage network with a reference voltage that feeds back to the VREFCA input of every component on the flyby chain. Intel® Agilex™ FPGA circuitry cannot compensate for discontinuities or trace length mismatches along the flyby chain, or for crosstalk between address/command or DQ signals.

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