External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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10.4.8. Data Reordering

Data reordering and command reordering can both contribute towards achieving controller efficiency.

The Data Reordering feature allows the single-port memory controller to change the order of read and write commands to achieve highest efficiency. You can enable data reordering by turning on Enable Reordering on the Controller Settings tab of the parameter editor.

In the soft memory controller, inter-bank data reordering serves to minimize bus turnaround time by optimizing the ordering of read and write commands going to different banks; commands going to the same bank address are not reordered.

Figure 165. Data Reordering for Minimum Bus Turnaround

Data Reordering for Minimum Bus Turnaround

In the hard memory controller, inter-row data reordering serves to minimize tRC by reordering commands going to different bank and row addresses; commands going to the same bank and row address are not reordered. Inter-row data reordering inherits the minimum bus turnaround time benefit from inter-bank data reordering.

Figure 166. Data Reordering for Minimum tRC

Data Reordering for Minimum tRC

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