External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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Document Table of Contents

5.3.6. Running the Simulation

Modifying the vcs_setup.sh File

In a text editor, modify the vcs_setup.sh file to include the IP/files required for simulation. Referring to the following sample, add the lines shown in bold italics, to the vcs_setup.sh file generated by the Intel® Quartus® Prime software:

# QIP stuff
MENTOR_VIP_AE=${QUARTUS_INSTALL_DIR}/../ip/altera/mentor_vip_ae
export QUESTA_MVC_GCC_LIB=${MENTOR_VIP_AE}/common/questa_mvc_core/\
linux_x86_64_gcc-6.2.0_vcs
export LDFLAGS="-L ${QUESTA_MVC_GCC_LIB} -Wl,-rpath ${QUESTA_MVC_GCC_LIB}\
-laxi4_IN_SystemVerilog_VCS_full_DVC"

vcs -lca -timescale=1ps/1ps -sverilog +verilog2001ext+.v $ELAB_OPTIONS $USER_DEFINED_ELAB_OPTIONS \
  +systemverilogext+.sv +vpi -debug_access+r+w+nomemcbk +vcs+lic+wait \
  -cpp /usr/intel/pkgs/gcc/6.2.0/bin/g++ \
  -l vcs.log -kdb \
  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_primitives.v \
  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/220model.v \
  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/sgate.v \
  -v $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_mf.v \
  $MENTOR_VIP_AE/common/questa_mvc_svapi.svh \
  $MENTOR_VIP_AE/axi4/bfm/mgc_common_axi4.sv \
  $MENTOR_VIP_AE/axi4/bfm/mgc_axi4_monitor.sv \
  $MENTOR_VIP_AE/axi4/bfm/mgc_axi4_inline_monitor.sv \
  $MENTOR_VIP_AE/axi4/bfm/mgc_axi4_slave.sv \
  $MENTOR_VIP_AE/axi4/bfm/mgc_axi4_master.sv \
  ./../../master_test_program.sv \
  $QUARTUS_INSTALL_DIR/eda/sim_lib/altera_lnsim.sv \
  $QUARTUS_INSTALL_DIR/eda/sim_lib/fourteennm_atoms.sv \
  $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/fourteennm_atoms_ncrypt.sv \
  $QUARTUS_INSTALL_DIR/eda/sim_lib/ct1_hssi_atoms.sv \
  $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/ct1_hssi_atoms_ncrypt.sv \
  $QUARTUS_INSTALL_DIR/eda/sim_lib/ct1_hip_atoms.sv \
  $QUARTUS_INSTALL_DIR/eda/sim_lib/synopsys/ctp_hssi_atoms_ncrypt.sv \
  $common_design_files \
  $design_files \
  $USER_DEFINED_ELAB_OPTIONS_APPEND \
  -top $TOP_LEVEL_NAME

Running the Simulation

To run the simulation, follow these steps:

  1. Change directory to the /vcs folder:
    cd <example_design_path>/sim/ed_sim/sim/synopsys/vcs
  2. Type the following command to run the simulation:
    source ./vcs_setup.sh USER_DEFINED_ELAB_OPTIONS="+vcs+vcdpluson" USER_DEFINED_SIM_OPTIONS=""  | tee out.txt

Example Simulation Result

Upon successful completion, you should see simulation output similar to the following, at the terminal:
[300427058] [DWR=000]:  Reading data ace6ace7ace4ace5 @ 10000001 (CGBRC=0/1/0/0/0 ) burst 1
[300427478] [DWR=000]:  Reading data aceaacebace8ace9 @ 10000002 (CGBRC=0/1/0/0/0 ) burst 2
[300427898] [DWR=000]:  Reading data 0000000000000000 @ 10000003 (CGBRC=0/1/0/0/0 ) burst 3
[300428318] [DWR=000]:  Reading data 0000000000000000 @ 10000004 (CGBRC=0/1/0/0/0 ) burst 4
[300428738] [DWR=000]:  Reading data 0000000000000000 @ 10000005 (CGBRC=0/1/0/0/0 ) burst 5
[300429158] [DWR=000]:  Reading data 0000000000000000 @ 10000006 (CGBRC=0/1/0/0/0 ) burst 6
[300429578] [DWR=000]:  Reading data 0000000000000000 @ 10000007 (CGBRC=0/1/0/0/0 ) burst 7
@            300498240, master_test_program: Read correct data (hACE0ACE1) at address (64)
@            300498240, master_test_program: Read correct data (hACE2ACE3) at address (68)
@            300498240, master_test_program: Read correct data (hACE4ACE5) at address (72)
$finish called from file "./../../master_test_program.sv", line 375.
$finish at simulation time            300508240
           V C S   S i m u l a t i o n   R e p o r t 
Time: 300508240 ps
CPU Time:    400.970 seconds;       Data structure size:  55.3 Mb