External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

4.1.2.16. emif_calbus_clk for QDR-IV

EMIF calibration component clock input interface
Table 55.  Interface: emif_calbus_clkInterface type: Clock Output
Port Name Direction Description
calbus_clk Output EMIF Calibration component bus for the clock

Did you find the information on this page useful?

Characters remaining:

Feedback Message