External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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11.3.1. Evaluating FPGA Timing Issues

Usually, you should not encounter timing issues with Intel® -provided IP unless your design exceeds Intel® 's published performance range or you are using a device for which the Intel® Quartus® Prime software offers only preliminary timing model support. Nevertheless, timing issues can occur in the following circumstances:
  • The .sdc files are incorrectly added to the Intel® Quartus® Prime project
  • Intel® Quartus® Prime analysis and synthesis settings are not correct
  • Intel® Quartus® Prime Fitter settings are not correct

For all of these issues, refer to the correct user guide for more information about recommended settings, and follow these steps:

  1. Ensure that the IP generated .sdc files are listed in the Intel® Quartus® Prime Timing Analyzer files to include in the project window.
  2. Configure the Settings as follows, to help close timing in the design:
      1. On the Assignments menu click Settings.
      2. In the Category list, click Compiler Settings.
      3. Select Optimization mode > Performance > High Performance Effort.
      1. On the Assignments menu click Settings.
      2. In the Category list, click Compiler Settings > Advanced Settings (Synthesis)..
      3. For Optimization Technique, select Speed.
      1. On the Assignments menu click Settings.
      2. In the Category list, click Compiler Settings > Advanced Settings (Fitter).
      3. For Physical Placement Effort, select High Effort/Maximum Effort.
  3. Use Timing Analyzer Report Ignored Constraints, to ensure that .sdc files are successfully applied.
  4. Use Timing Analyzer Report Unconstrained Paths, to ensure that all critical paths are correctly constrained.

More complex timing problems can occur if any of the following conditions are true:

  • The design includes multiple PHY or core projects
  • Devices where the resources are heavily used
  • The design includes wide, distributed, maximum performance interfaces in large die sizes

Any of the above conditions can lead to suboptimal placement results when the PHY or controller are distributed around the FPGA. To evaluate such issues, simplify the design to just the autogenerated example top-level file and determine if the core meets timing and you see a working interface. Failure implies that a more fundamental timing issue exists. If the standalone design passes core timing, evaluate how this placement and fit is different than your complete design.

Use LogicLock regions or design partitions to better define the placement of your memory controllers. When you have your interface standalone placement, repeat for additional interfaces, combine, and finally add the rest of your design.

Additionally, use fitter seeds and increase the placement and router effort multiplier.

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