External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022

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7.1.6. Intel Agilex EMIF IP QDR-IV Parameters: Diagnostics

Table 137.  Group: Diagnostics / Simulation Options
Display Name Description
Calibration mode Specifies whether to skip memory interface calibration during simulation, or to simulate the full calibration process.

Simulating the full calibration process can take hours (or even days), depending on the width and depth of the memory interface. You can achieve much faster simulation times by skipping the calibration process, but that is only expected to work when the memory model is ideal and the interconnect delays are zero.

If you enable this parameter, the interface still performs some memory initialization before starting normal operations. Abstract PHY is supported with skip calibration.

Table 138.  Group: Diagnostics / Calibration Debug Options
Display Name Description
Skip VREF_in calibration Specifies to skip the VREF stage of calibration. Enable this parameter for debug purposes only; generally, you should include the VREF calibration stage during normal operation. (Identifier: DIAG_QDR4_SKIP_VREF_CAL)
Table 139.  Group: Diagnostics / Example Design
Display Name Description
Enable In-System-Sources-and-Probes Enables In-System-Sources-and-Probes in the example design for common debug signals, such as calibration status or example traffic generator per-bit status. This parameter must be enabled if you want to do driver margining using the EMIF Debug Toolkit. (Identifier: DIAG_QDR4_EX_DESIGN_ISSP_EN)
Table 140.  Group: Diagnostics / Performance
Display Name Description
Efficiency Monitor Mode Adds an Efficiency Monitor component to the Avalon-MM interface of the memory controller, allowing you to view efficiency statistics of the interface. You can access the efficiency statistics using the EMIF Efficiency Monitor Toolkit. (Identifier: DIAG_QDR4_EFFICIENCY_MONITOR)
Table 141.  Group: Diagnostics / Miscellaneous
Display Name Description
Export PLL lock signal Specifies whether to export the pll_locked signal at the IP top-level to indicate status of PLL. (Identifier: DIAG_EXPORT_PLL_LOCKED)