External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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4.2.3. AFI Write Data Signals

Write Data Signals for AFI 4.0 control the data, data mask, and strobe signals passed to the memory device during write operations.
Table 58.  Write Data Signals

Signal Name

Direction

Width

Description

afi_dqs_burst

Input

AFI_RATE_RATIO

Controls the enable on the strobe (DQS) pins for memory devices. When this signal is asserted, mem_dqs and mem_dqsn are driven.

This signal must be asserted before afi_wdata_valid to implement the write preamble, and must be driven for the correct duration to generate a correctly timed mem_dqs signal.

afi_wdata_valid

Input

AFI_RATE_RATIO

Write data valid signal. This signal controls the output enable on the data and data mask pins.

afi_wdata

Input

AFI_DQ_WIDTH

Write data signal to send to the memory device at double-data rate. This signal controls the PHY’s mem_dq output.

afi_dm

Input

AFI_DM_WIDTH

Data mask.

Also directly controls the PHY's mem_dbi signal for DDR4.

The mem_dm and mem_dbi features share the same port on the memory device.

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