External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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9.8. Multi-Rank Topology

The Intel® Agilex™ FPGA EMIF I/O timing collateral supplies simulation deck variants that allow you to evaluate the termination settings for multi-rank memory interfaces. For DDR4 multi-rank interfaces, simulation scenarios are provided to target every rank in the system. Non-target ranks provide idle termination as specified by the RTT_NOM and RTT_PARK ODT values for in the EMIF IP as well as the ODT activation matrices.

The simulation decks for multi-rank designs use different top-level files:

  • For write operations, the files dq_2rank_wr_top.sp, dq_4rank_wr_top.sp implement the simulation deck for 2-rank and 4-rank interfaces, respectively.
  • For read operations, the files dq_2rank_rd_top.sp and dq_4rank_rd_top.sp implement the simulation decks.

The ALTER construct is used to modify the SPICE deck to exercise different target ranks, which facilitates parallel simulations in most SPICE simulators. You must evaluate the data eyes for compliance at each target rank.

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