External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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9.10. Mask Evaluation

After you have completed each of the three simulations, eye diagrams must be generated at the receiver IBIS model for each of the victim pins; you must check these eye diagrams against compliance masks supplied by the IP. This topic explains how to capture the eye diagram.
Note: Final masks will be available in a later version of the Intel® Quartus® Prime software. To obtain compliance masks for ES revisions of Intel® Agilex™ devices, you should contact Intel® .

For each of the simulation decks listed below, the probe point for evaluation is located at the IBIS receiver node. This node can be found by navigating to the lane_rx12 instance of the desired component/rank, expanding to find the victim rx_buffer instance, and locating the ibis node. The data_out nodes of the IBIS models are not used for eye diagram evaluation.

For SSTL and other center-tap-terminated I/O standards, the mask is centered about the termination voltage; however for POD I/O standards, you may need to shift the mask vertically to account for dynamically-calibrated reference voltages.

Address/Command Eyes

You must evaluate the address/command data eye at every victim pin for every component in the interface, including all components in the fly-by chain, and every rank in the system. You should capture the eye for each component using a trigger of the crossing point of the rising and falling edges of the memory clock pin measured at the IBIS model nodes in the same component.

Data Write Eyes

You must evaluate the write data eye at every victim pin for all possible target DQ ranks in the interface. You should capture the eye at the memory for each component, using a trigger of the crossing point of the rising and falling edge of the DQS write strobes measured at the IBIS model nodes in the same component.

Data Read Eyes

You must evaluate the read data eyes using the victim pin at the FPGA, for all possible target DQ ranks in the interface. You should capture the eye using the crossing point of the rising and falling edges of the complementary DQS strobe as measured at the IBIS model nodes at the FPGA.

Mask Properties

The masks supplied by the IP for address/command and FPGA write operations are constructed using the JEDEC specifications as a starting point. The masks are then enlarged to account for the following effects from the FPGA:

  • Memory Clock / Transmit strobe jitter
  • Worst-case FPGA package cross-talk effects
  • Worst-case temperature drift variations
  • Calibrated termination uncertainty
  • Output delay chain variations
  • Calibrated voltage reference uncertainty
  • Package PDN effects
  • Process variation
  • Volume data collection

For FPGA read operations, the following additional effects are incorporated into the receiver mask:

  • Input delay chain jitter
  • Input delay chain INL/DNL error
  • Calibration algorithm uncertainty

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