External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

7.3.2.1. OCT

You require an OCT calibration block if you are using an Intel® Agilex™ FPGA OCT calibrated series, parallel, or dynamic termination for any I/O in your design. There are two OCT blocks in an I/O bank, one for each sub-bank.

You must observe the following requirements when using OCT blocks:

  • The I/O bank where you place the OCT calibration block must use the same VCCIO_PIO voltage as the memory interface.
  • The OCT calibration block uses a single fixed RZQ . You must ensure that an external termination resistor is connected to the correct pin for a given OCT block.

Did you find the information on this page useful?

Characters remaining:

Feedback Message