External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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4.1.1.20. ctrl_ecc_readdataerror for DDR4

Controller ECC read data error indication interface
Table 33.  Interface: ctrl_ecc_readdataerrorInterface type: Conduit
Port Name Direction Description
ctrl_ecc_readdataerror Output Signal is asserted high by the controller ECC logic to indicate that the read data has an uncorrectable error. The signal has the same timing as the read data valid signal of the Controller Avalon Memory-Mapped interface.

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