External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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6.1.8. Intel Agilex EMIF IP DDR4 Parameters: Example Designs

Table 98.  Group: Example Designs / Example Designs with Multi-IPs
Display Name Description
Simulation Specifies that the 'Generate Example Design' button create all necessary file sets for simulation. Expect a short additional delay as the file set is created. If you do not enable this parameter, simulation file sets are not created. Instead, the output directory contains the ed_sim.qsys file which holds Platform Designer details of the simulation example design, and a make_sim_design.tcl file with other corresponding tcl files. You can run make_sim_design.tcl from a command line to generate the simulation example design. The generated example designs for various simulators are stored in the /sim sub-directory. (Identifier: EX_DESIGN_GUI_DDR4_GEN_SIM)
Synthesis Specifies that the 'Generate Example Design' button create all necessary file sets for synthesis. Expect a short additional delay as the file set is created. If you do not enable this parameter, synthesis file sets are not created. Instead, the output directory contains the ed_synth.qsys file which holds Platform Designer details of the synthesis example design, and a make_qii_design.tcl script with other corresponding tcl files. You can run make_qii_design.tcl from a command line to generate the synthesis example design. The generated example design is stored in the /qii sub-directory. (Identifier: EX_DESIGN_GUI_DDR4_GEN_SYNTH)
Signal Integrity Specifies that the 'Generate Example Design' button create all necessary collateral for performing Signal Integrity analysis with a third-party analog simulation tool. Expect a short additional delay as the file set is created. If you do not enable this parameter, board simulation collateral is not created. The generated collateral is stored in the /bsi sub-directory. Note that this option is only supported for selected memory protocols on the Agilex family. (Identifier: EX_DESIGN_GUI_DDR4_GEN_BSI)
Spyglass CDC Specifies that the Generate Example Design button create all necessary files for performing CDC analysis with Spyglass. Expect a short additional delay as the file set is created. If you do not enable this parameter, CDC file sets simulation are not created. The generated collateral is stored in the /cdc sub-directory. Note that this option is only supported for selected memory protocols. (Identifier: EX_DESIGN_GUI_DDR4_GEN_CDC)
Simulation HDL format This option lets you choose the format of HDL in which generated simulation files are created. (Identifier: EX_DESIGN_GUI_DDR4_HDL_FORMAT)
Number of IPs Specifies the number of EMIF IPs to instantiate in the example designs. All the IPs have individual TGs and can be connected to one of the available Cal-IPs.
EMIF ID Specifies the number of EMIF IP that you want in the Multi-IP design. Depending on the size of the EMIF interface, you can have up to 16 EMIF interfaces.
CAL-IP Specifies the Calibration IP to which a given EMIF should connect in the example design. All the EMIF IPs must be connected to one of the available Cal-IPs. There are two Calibration IPs on the device. Each of the EMIF IP must be connected to either of the two Cal-IPs.
Capture The capture button allows you to take a capture of the current EMIF IP settings and apply to given EMIF ID interface.
Table 99.  Group: Example Designs / Target Development Kit
Display Name Description
Select board Specifies that when you select a development kit with a memory module, the generated example design contains all settings and fixed pin assignments to run on the selected board. You must select a development kit preset to generate a working example design for the specified development kit. Any IP settings not applied directly from a development kit preset do not have guaranteed results when testing the development kit. To exclude hardware support of the example design, select 'none' from the 'Select board' pull down menu. When you apply a development kit preset, all IP parameters are automatically set appropriately to match the selected preset. If you want to save your current settings, you should do so before you apply the preset. You can save your settings under a different name using File->Save as. (Identifier: EX_DESIGN_GUI_DDR4_TARGET_DEV_KIT)

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