184.108.40.206. Clock Signals
- tDQSCK is the skew between the CK or CK# signals and the SDRAM-generated DQS signal
- tDSH is the DQS falling edge from CK rising edge hold time
- tDSS is the DQS falling edge from CK rising edge setup time
- tDQSS is the positive DQS latching edge to CK rising edge
SDRAM devices have a write requirement (tDQSS) that states the positive edge of the DQS signal on writes must be within ± 25% (± 90°) of the positive edge of the SDRAM clock input. Therefore, you should generate the CK and CK# signals using the DDR registers in the IOE to match with the DQS signal and reduce any variations across process, voltage, and temperature. The positive edge of the SDRAM clock, CK, is aligned with the DQS write to satisfy tDQSS.
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