10.4.1.1. Using Auto-precharge to Achieve Highest Memory Bandwidth for DDR4 Interfaces
Regardless of how many DDR4 bank groups are open for a series of Avalon® memory-mapped interface accesses to the controller, the auto-precharge takes effect only on the last beat of the Avalon® memory-mapped interface burst.
In each of the following cases, you would use long bursts of sequentially addressed read or write traffic data patterns and the auto-precharge when an access is the last to a memory page. (A memory page is defined as a bank group, bank address and row address combination that is opened by a DDR4 activate command). Long bursts at the DDR4 memory can originate from either an Avalon® access with a large burst size or sequentially addressed Avalon® accesses of smaller burst sizes. The controller open page policy keeps the memory page open so it can sustain back-to-back accesses at the DDR4 memory.
The DDR4 IP is configured with the Efficiency > Address ordering parameter on the Controller tab. You can set this value to CS-CID-Row-Bank-Col-BG or CID-Row-CS-Bank-Col-BG.
Break your Avalon® accesses to the DDR4 hard controller into sequentially addressed accesses with a burst size of 1. Four bank groups are used, and for the final four accesses, assert the auto-precharge signal so that all of the bank groups receive read or write with auto-precharge commands. DDR4 devices with x4 and x8 configurations have four bank groups. (DDR4 x16 devices have only two bank groups.)
The DDR4 IP is configured with the Efficiency > Address ordering parameter on the Controller tab set to CS-BG-Bank-CID-Row-Col. With this address ordering, only one memory page is opened and you can use Avalon® burst accesses with burst sizes greater than one. For the last access in the burst, assert the auto-precharge signal.
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