External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.5.6.2. Single Rank x 16 Discrete (Component) Topology

Five memory devices are required to cover 72 bits of data in a single channel, with one rank and ×16 memory devices.

The interface covers data bytes (DQ/DQS), address signals, command signals (BA, BG, RAS, CAS, WE, ACT, PAR), control signals (CKE, CS, ODT) and clocks (CLK).

Figure 132. Signal connections for DDR4 Single Rank × 16 Discrete Topology (5 memory devices to cover 72 bits)
Table 115.  Specific Routing Guidelines for Single Rank x16 Discrete Memory Topology for All Supported Signals in the Interface
Signal Group Segment Routing Layer Max Length (mil) Target Zse (ohm) Trace Width, W (mil) Trace Spacing, S1 (mil): Within Group Trace Spacing, S2 (mil): CMD/CTRL/CLK to DQ/DQS Trace Spacing, S3 (mil): DQ Nibble to Nibble Trace Spacing (mil), Within DIFF pair Trace Spacing (mil), DQS pair to DQ Trace Spacing (mil), CLK pair to CMD/CTRL/CKE Rtt / Ctt
Segment Total MB
CLK BO1 US 50 To first DRAM: 4000. To last DRAM: 6800.   4 5, 17 17   4   17 R1=36Ω. C1=10nF
BO2 SL 1000   4 5, 17 17   4   17
M SL   40 5.5   12 (3h)   4   12 (3h)
BI1 US 50   3   12 (3h)   4   12 (3h)
BI2 SL 700 50 3   12 (3h)   4   12 (3h)
T1 SL 300   3   12 (3h)   4   12 (3h)
T2 US 50   3   12 (3h)   4   12 (3h)
CMD, CTRL, Alert BO1 US 50 To first DRAM: 4000. To last DRAM: 6800.   4 5, 17 17         R1=36Ω

alert_n requires an external pullup resistor to VDD (1.2V) of approximately 10KΩ.
BO2 SL 1000   4 5, 17 17        
M SL   40 5.5 8 (2H) 12 (3h)        
BI1 US 50   3 8 (2H) 12 (3h)        
BI2 SL 700 50 3 8 (2H) 12 (3h)        
T1 SL 300   3 8 (2H) 12 (3h)        
T2 US 50   3 8 (2H) 12 (3h)        
DQ BO1 US 50 5000   4 5, 17   17        
BO2 SL 1000   4 5, 17   17      
M SL   45 4.5 8 (2H)   12 (3h)      
BI US 50   4 8 (2H)   12 (3h)      
DQS BO1 US 50 5000   4       4 17    
BO2 SL 1000   4       4 17  
M SL   45 4.5       4 12 (3h)  
BI US 50   4       4 12 (3h)  
For an explanation of the guidelines represented in this table, refer to the bullet points immediately following Figure 122.

Did you find the information on this page useful?

Characters remaining:

Feedback Message