External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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4.1.1.18. ctrl_user_priority for DDR4

Controller user-requested priority interface
Table 31.  Interface: ctrl_user_priorityInterface type: Conduit
Port Name Direction Description
ctrl_user_priority_hi Input When asserted high along with a read or write request to the memory controller, indicates that the request is high priority and should be fulfilled before other low priority requests.

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