External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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3.3.1. Intel® Agilex™ Calibration Stages

At a high level, the calibration routine consists of address and command calibration, read calibration, and write calibration.

The stages of calibration vary, depending on the protocol of the external memory interface.

Table 8.  Calibration Stages by Protocol
Stage DDR4 QDR-IV
Address and Command
Leveling Yes
Deskew Yes Yes
Read
DQSen Yes Yes
Deskew Yes Yes
VREF-In Yes Yes
LFIFO Yes Yes
Write
Leveling Yes Yes
Deskew Yes Yes
VREF-Out Yes

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