External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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9.9. Pin Parasitics

The IBIS support in SPICE does not permit using the RLC parasitic data embedded within the IBIS model, therefore a separate include file is provided for annotating pin parasitic data for both the memory-side and FPGA-side package pins. This include file is named pin_parasitics.dat and is initially set to 0 for all values of parasitic pin resistance, inductance and capacitance.

You can annotate the values in the pin_parasitics.dat file with the appropriate package parasitic information once the exact placement and package types are determined. (Note that this file assumes that the same memory component is used throughout the interface, meaning that only one set of RLC values per memory package pin is supported – 12 values for each pin in the Address/Command channel, and 12 values for each pin in the DQ channel.)

You can obtain pin parasitic information for Intel® Agilex™ FPGAs from the Intel® website. You can extract parasitic information for the memory models from the Component section of the IBIS model file. Note that the pins corresponding to the signals of the 12-line extractions for the AC and DQ paths should be used for both the memory and the FPGA.

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