External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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Document Table of Contents

10.1. Interface Standard

Complying with certain interface standard specifications affects controller efficiency.

When interfacing the memory device to the memory controller, you must observe timing specifications and perform the following bank management operations:

  • Activate

    Before you issue any read (RD) or write (WR) commands to a bank within an SDRAM device, you must open a row in that bank using the activate (ACT) command. After you open a row, you can issue a read or write command to that row based on the tRCD specification. Reading or writing to a closed row has negative impact on the efficiency as the controller has to first activate that row and then wait until tRCD time to perform a read or write.

  • Precharge

    To open a different row in the same bank, you must issue a precharge command. The precharge command deactivates the open row in a particular bank or the open row in all banks. Switching a row has a negative impact on the efficiency as you must first precharge the open row, then activate the next row and wait tRCD time to perform any read or write operation to the row.

  • Device CAS latency

    The memory device has its own read latency, and the higher the CAS latency, the less efficient an individual access. The higher the operating frequency, the longer the CAS latency is in number of cycles.

  • Refresh

    A refresh, in terms of cycles, consists of the precharge command and the waiting period for the auto refresh.

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