External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.5.1.4. On-Chip Termination Recommendations for Intel® Agilex™ FPGA Devices

In the EMIF IP parameter editor you can select values from drop-down lists for each of the following:

  • output mode drive strength for the address/command bus.
  • output mode drive strength for the memory clock.
  • output mode drive strength for the data bus.
  • input mode termination strength for the data bus.

The range of available values may vary, depending on your memory protocol and silicon revision.

You can use the default values as starting points; however, for best results, you should sweep the entire range of legal values and generate multiple hardware designs to determine the optimal settings for your board and memory device. The optimal settings are those that yield the largest margin as measured by the Driver Margining tool.

Once you have found the optimal settings for your design, uncheck the Use Default I/O settings checkbox and use your optimal settings for all future compilations, even if those settings align with the default settings. This ensures that your settings are preserved if the IP is upgraded to a future version.

Did you find the information on this page useful?

Characters remaining:

Feedback Message