External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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9.2. Collateral Generated with Your EMIF IP

The SPICE simulation files that you need to evaluate I/O timing closure are generated automatically as part of the EMIF IP file set.

IP options that affect electrical behavior are translated into parameters that are consumed by SPICE simulation decks to ensure that the analog simulation matches the IP configuration; these parameters include the following:

  • FPGA
    • On-chip termination settings
    • Slew rate and deemphasis settings
    • Multi-rank ODT settings
    • Memory clock frequency
    • Clock and strobe settings and phases
    • IBIS model configuration
  • Memory
    • Number of components and topology
    • IBIS model configuration
    • Clock and strobe settings and phases

The generated SPICE simulation decks allow for evaluation of the address/command channel, the FPGA-to-Memory write channel, and the Memory-to-FPGA read channel. The resulting data eye for each of these simulations is evaluated against a compliance mask supplied by the IP to determine whether the channel crosstalk, ISI and loss characteristics are adequate for the desired operating frequency.

The simulation decks are constructed in a way that allows you to replace default transmission-line models with S-parameter touchstone extractions of the PCB for channel evaluation. The system assumes that you have followed the PCB design guidelines for trace length, geometry, and spacing as closely as possible, and have determined the dielectric material and stackup of your PCB.

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