External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

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4.4.8. caltiming3

address=34(32 bit)

Field Bit High Bit Low Description Access
cfg_t_param_wr_to_wr_diff_bg 5 0 Write to write command timing on different bank groups. Read
cfg_t_param_wr_to_rd 11 6 Write to read command timing. Read
cfg_t_param_wr_to_rd_diff_chip 17 12 Write to read command timing on different chips. Read
cfg_t_param_wr_to_rd_diff_bg 23 18 Write to read command timing on different bank groups. Read
cfg_t_param_wr_to_pch 29 24 Write to precharge command timing. Read

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