3.1.4. Intel® Agilex™ EMIF Architecture: I/O Lane
|Pin Index||Lane||Sub-bank Location|
Each I/O lane can implement one x8/x9 read capture group (DQS group), with two pins functioning as the read capture clock/strobe pair (DQS/DQS#), and up to 10 pins functioning as data pins (DQ and DM pins). To implement a x18 group, you can use multiple lanes within the same sub-bank.
It is also possible to implement a pair of x4 groups in a lane. In this case, four pins function as clock/strobe pair, and 8 pins function as data pins. DM is not available for x4 groups. There must be an even number of x4 groups for each interface.
For x4 groups, DQS0 and DQS1 must be placed in the same I/O lane as a pair. Similarly, DQS2 and DQS3 must be paired. In general, DQS(x) and DQS(x+1) must be paired in the same I/O lane.
For DQ and DQS pin assignments for various configurations, refer to the Intel® Agilex™ device pin tables at the following location: https://www.intel.com/content/www/us/en/programmable/support/literature/lit-dp.html.
|Group Size||Number of Lanes Used||Maximum Number of Data Pins per Group|
|x8 / x9||1||10|
|pair of x4||1||4 per group, 8 per lane|
Did you find the information on this page useful?