5.3.1. Overview of Steps
If you are creating the design with other DQ width, the DQ width of the EMIF IP must be one of 8,16,32 or 64. If this requirement is not met, the Platform Designer issues an error similar to the following, when you connect the AXI4 master BFM to the EMIF IP:
ed_sim.emif_fm_0.ctrl_amm_0 Date width must be of power of two and between 8 and 4096.
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