External Memory Interfaces Intel® Agilex™ FPGA IP User Guide

ID 683216
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.3.1. Overview of Steps

The following figure shows the overall steps and changes required in the simulation design example, to perform functional simulation with the Mentor Graphics* AXI4 Master BFM (Intel FPGA Edition).
Figure 98. Steps to Simulate Design Example with the Mentor Graphics* AXI4 Master BFM (Intel FPGA Edition)

If you are creating the design with other DQ width, the DQ width of the EMIF IP must be one of 8,16,32 or 64. If this requirement is not met, the Platform Designer issues an error similar to the following, when you connect the AXI4 master BFM to the EMIF IP:

ed_sim.emif_fm_0.ctrl_amm_0		Date width must be of power of two and between 8 and 4096.

Did you find the information on this page useful?

Characters remaining:

Feedback Message