Stratix V Device Handbook: Volume 2: Transceivers

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ID 683779
Date 11/23/2021
Public
Document Table of Contents

4.7.4.2. Using the coreclkin Ports

The tx_coreclkin and rx_coreclkin ports offer the flexibility to use the tx_clkout and rx_clkout from one channel to clock the TX and RX FIFOs multiple channels for source synchronous links or if the upstream transmitters are all clocked by the same clock source. The tx_coreclkin and rx_coreclkin ports require a zero ppm difference between the tx_clkout and rx_clkout ports, respectively, with a divided-by-50 input frequency.

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