Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Document Table of Contents

3.2.3. Resetting the Transmitter with the User-Coded Reset Controller During Device Operation

Follow this reset sequence if you want to reset the PLL, or analog or digital blocks of the transmitter at any point during device operation. This might be necessary for re-establishing a link or after certain dynamic reconfigurations.

The numbers in the following figure correspond to the following numbered list, which guides you through the transmitter reset sequence during device operation.

  1. To reset the transmitter:
    • Assert pll_powerdown, tx_analogreset and tx_digitalreset. tx_digitalreset must be asserted every time pll_powerdown and tx_analogreset are asserted to reset the PCS blocks.
    • Hold pll_powerdown asserted for a minimum duration of tpll_powerdown.
    • Deassert tx_analogreset at the same time or after pll_powerdown is deasserted.
  2. After the transmitter PLL locks, the pll_locked status is asserted after tpll_lock. While the TX PLL locks, the pll_locked status signal may toggle. It is asserted after tpll_lock.
  3. Deassert tx_digitalreset after a minimum duration of ttx_digitalreset, and after all the gating conditions are removed:
    • pll_powerdown is deasserted
    • pll_locked is deasserted
Figure 82.  Reset Sequence Timing Diagram for Transmitter using the User-Coded Reset Controller during Device Operation