Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

2.2.3.1. GX Channel Receiver Clocking

Figure 64. Receiver 10G PCS and PMA Clocking


Figure 65. Receiver Standard PCS and PMA Clocking


The CDR in the PMA of each channel recovers the serial clock from the incoming data. The CDR also divides the serial clock (recovered) to generate the parallel clock (recovered). Both clocks are used by the deserializer. The receiver PCS can use the following clocks, depending on the configuration of the receiver channel:

  • Parallel clock (recovered) from the CDR in the PMA
  • Parallel clock from the clock divider used by the transmitter PCS for that channel
Table 18.  Clock Sources for All Receiver PCS Blocks
PCS Block Clock Source
Standard Word aligner Parallel clock (recovered)
Rate match FIFO
  • Write side: parallel clock (recovered)
  • Read side: parallel clock from the clock divider
8B/10B decoder
  • If rate matcher is not used: parallel clock (recovered)
  • If rate matcher is used: parallel clock from the clock divider
Byte deserializer Write side:
  • If rate matcher is not used: parallel clock (recovered)
  • If rate matcher is used: parallel clock from the clock divider
Read side: Divided down version of the write side clock, depending on the deserialization factor of 1 or 2, also called the parallel clock (divided)
Byte ordering Parallel clock (divided)
Receiver (RX) phase compensation FIFO
  • Write Side: Parallel clock (divided). This clock is also forwarded to the FPGA fabric
  • Read Side: Clock sourced from the FPGA fabric
10G All PCS blocks
  • Regular mode: parallel clock (recovered)
  • Loopback mode: parallel clock from the clock divider7
7 For more information about loopback mode, refer to the Transceiver Loopback Support in Stratix V Devices chapter.

Did you find the information on this page useful?

Characters remaining:

Feedback Message