Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

3.1. PHY IP Embedded Reset Controller

The embedded reset controller in the PHY IP enables you to initialize the transceiver physical coding sublayer (PCS) and physical medium attachment (PMA) blocks.

To simplify your transceiver-based design, the embedded reset controller provides an option that requires only one control input to implement an automatic reset sequence. Only one embedded reset controller is available for all the channels in a PHY IP instance.

The embedded reset controller automatically performs the entire transceiver reset sequence whenever the phy_mgmt_clk_reset signal is triggered. In case of loss-of-link or loss-of-data, the embedded reset controller asserts the appropriate reset signals. You must monitor tx_ready and rx_ready. A high on these status signals indicates the transceiver is out of reset and ready for data transmission and reception.

Note: Deassert the mgmt_rst_reset signal of the transceiver reconfiguration controller at the same time as phy_mgmt_clk_reset to start calibration.
Note: You must have a valid and stable ATX PLL reference clock before deasserting the phy_mgmt_clk_reset and mgmt_rst_reset signals for successful ATX PLL calibration.
Note: The PHY IP embedded reset controller is enabled by default in all transceiver PHY IP cores except the Native PHY IP core.

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