3.1. PHY IP Embedded Reset Controller
To simplify your transceiver-based design, the embedded reset controller provides an option that requires only one control input to implement an automatic reset sequence. Only one embedded reset controller is available for all the channels in a PHY IP instance.
The embedded reset controller automatically performs the entire transceiver reset sequence whenever the phy_mgmt_clk_reset signal is triggered. In case of loss-of-link or loss-of-data, the embedded reset controller asserts the appropriate reset signals. You must monitor tx_ready and rx_ready. A high on these status signals indicates the transceiver is out of reset and ready for data transmission and reception.
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