Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

4.7.2. Standard PCS Configurations—Low Latency Datapath

A low latency datapath bypasses much of the standard PCS, allowing more design control in the FPGA fabric. Use the Low Latency PHY IP to enable the standard PCS in a low latency datapath.

To implement a Low Latency PHY link, instantiate the Low Latency PHY IP in the IP Catalog, under Transceiver PHY in the Interfaces menu. In the Low Latency GUI under the General tab, select Standard on the Datapath type field.

The standard PCS can be used in a low latency datapath that contains only the following blocks:

  • Phase compensation FIFO
  • Byte serializer and deserializer
Figure 143. Standard PCS Low Latency Datapath


You can divide the low latency datapath into two configurations based on the FPGA fabric-transceiver interface width and the PMA-PCS interface width (serialization factor):

  • Low latency 8/10-bit-width—the PCS-PMA interface width is in 8-bit or 10-bit mode for lower data rates.
  • Low latency 16/20-bit-width—the PCS-PMA interface width is in 16-bit or 20-bit mode for higher data rates.
Table 42.  PCS-PMA Interface Widths and Data Rates
Low Latency PHY IP Core Supported Data Rate Range PMA
Low Latency 8-bit width 600 Mbps to 5.20 Gbps
Low Latency 10-bit width 600 Mbps to 6.50 Gbps
Low Latency 16-bit width 600 Mbps to 9.76 Gbps
Low Latency 20-bit width 600 Mbps to 12.20 Gbps

In the low latency datapath, the TX and RX phase compensation FIFOs are always enabled. Depending on the targeted data rate, you may bypass the byte serializer and deserializer blocks.

Figure 144. Standard PCS Low Latency 8-Bit PMA-PCS Interface WidthShows the available options for the standard PCS low latency 8-bit PMA-PCS interface width. The blocks shown as “Disabled” are not used but incur latency. The blocks shown as “Bypassed” are not used and do not incur any latency. The maximum frequencies are for the fastest devices.


Figure 145. Standard PCS Low Latency 10-Bit PMA-PCS Interface WidthShows the available options for the standard PCS low latency 10-bit PMA-PCS interface width. The blocks shown as “Disabled” are not used but incur latency. The blocks shown as “Bypassed” are not used and do not incur any latency. The maximum frequencies are for the fastest devices.


Figure 146. Standard PCS Low Latency 16-Bit PMA-PCS Interface WidthShows the available options for the standard PCS low latency 16-bit PMA-PCS interface width. The blocks shown as “Disabled” are not used but incur latency. The blocks shown as “Bypassed” are not used and do not incur any latency. The maximum frequencies are for the fastest devices.


Figure 147. Standard PCS Low Latency 20-Bit PMA-PCS Interface WidthShows the available options for the standard PCS low latency 20-bit PMA-PCS interface width. The blocks shown as “Disabled” are not used but incur latency. The blocks shown as “Bypassed” are not used and do not incur any latency. The maximum frequencies are for the fastest devices.


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