Stratix V Device Handbook: Volume 2: Transceivers

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ID 683779
Date 11/23/2021
Public
Document Table of Contents

1.4.2.1. Transmitter FIFO

The transmitter FIFO provides an interface between the transmitter channel PCS and the FPGA fabric.

In 10GBASE-R configurations, the transmitter FIFO receives data from the FPGA fabric. The data output from the transmitter FIFO block goes to the 64B/66B encoder.

In Interlaken configurations, the transmitter FIFO sends a control signal to indicate whether it is ready to receive data from the FPGA fabric. The user logic sends the data to the transmitter FIFO only if this control signal is asserted. In this configuration, data output from the transmitter FIFO block goes to the frame generator.

Note: Altera recommends a minimum of 32 words for the soft FIFO depth in the FPGA fabric for the following conditions:
  • When the 10G PCS TX FIFO is set to register mode
  • When using the recovered clock to drive the core logics
  • When there is no soft FIFO being generated along with the IP Catalog

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