Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

2.3.1.2. Selecting a Transmitter Datapath Interface Clock

Multiple non-bonded transmitter channels use a large portion of GCLK, RCLK, and PCLK resources. Selecting a common clock driver for the transmitter datapath interface of all identical transmitter channels saves clock resources.

Multiple transmitter channels that are non-bonded lead to high utilization of GCLK, RCLK, and PCLK resources (one clock resource per channel). You can significantly reduce GCLK, RCLK, and PCLK resource use for transmitter datapath clocks if the transmitter channels are identical.

Note: Identical transmitter channels have the same input reference clock source, transmit PLL configuration, transmitter PMA, and PCS configuration, but may have different analog settings, such as transmitter voltage output differential (VOD), transmitter common-mode voltage (VCM), or pre-emphasis.

To achieve the clock resource savings, select a common clock driver for the transmitter datapath interface of all identical transmitter channels. The following figure shows eight identical channels clocked by a single clock (tx_clkout of channel 4).

Eight Identical Channels with a Single User-Selected Transmitter Interface Clock


To clock eight identical channels with a single clock, perform these steps:

  1. Instantiate the tx_coreclkin port for all the identical transmitter channels (tx_coreclkin[7:0]).
  2. Connect tx_clkout[4] to the tx_coreclkin[7:0] ports.
  3. Connect tx_clkout[4] to the transmitter data and control logic for all eight channels.
Note: Resetting or powering down channel 4 causes a loss of the clock for all eight channels.

The common clock must have a 0 ppm difference for the read side of the transmitter phase compensation FIFO of all the identical channels. A frequency difference causes the FIFO to under run or overflow, depending on whether the common clock is slower or faster, respectively.

You can drive the 0 ppm common clock by one of the following sources:

  • tx_clkout of any channel in non-bonded channel configurations
  • tx_clkout[0] in bonded channel configurations
  • When there is 0 PPM between refclk and tx_clkout
Note: The Quartus II software does not allow gated clocks or clocks that are generated in the FPGA logic to drive the tx_coreclkin ports.

You must ensure a 0 ppm difference. The Quartus II software is unable to ensure a 0 ppm difference because it allows you to use external pins, such as dedicated refclk pins.

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