126.96.36.199. Selecting a Transmitter Datapath Interface Clock
Multiple transmitter channels that are non-bonded lead to high utilization of GCLK, RCLK, and PCLK resources (one clock resource per channel). You can significantly reduce GCLK, RCLK, and PCLK resource use for transmitter datapath clocks if the transmitter channels are identical.
To achieve the clock resource savings, select a common clock driver for the transmitter datapath interface of all identical transmitter channels. The following figure shows eight identical channels clocked by a single clock (tx_clkout of channel 4).
To clock eight identical channels with a single clock, perform these steps:
- Instantiate the tx_coreclkin port for all the identical transmitter channels (tx_coreclkin[7:0]).
- Connect tx_clkout to the tx_coreclkin[7:0] ports.
- Connect tx_clkout to the transmitter data and control logic for all eight channels.
The common clock must have a 0 ppm difference for the read side of the transmitter phase compensation FIFO of all the identical channels. A frequency difference causes the FIFO to under run or overflow, depending on whether the common clock is slower or faster, respectively.
You can drive the 0 ppm common clock by one of the following sources:
- tx_clkout of any channel in non-bonded channel configurations
- tx_clkout in bonded channel configurations
- When there is 0 PPM between refclk and tx_clkout
You must ensure a 0 ppm difference. The Quartus II software is unable to ensure a 0 ppm difference because it allows you to use external pins, such as dedicated refclk pins.
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