4.4.2. Supported Features for PCIe Configurations
|x1, x2, x4, x8 link configurations||Yes||Yes||Yes|
|PCIe-compliant synchronization state machine||Yes||Yes||Yes|
|±300 ppm (total 600 ppm) clock rate compensation||Yes||Yes||Yes|
|8-bit FPGA fabric-transceiver interface (PIPE 2.0)||Yes||—||—|
|16-bit FPGA fabric-transceiver interface (PIPE 2.0)||Yes||Yes||—|
|32-bit FPGA fabric-transceiver interface (PIPE 3.0-like)||—||—||Yes|
|64-bit Hard IP Avalon-ST interface width (Hard IP only)||Yes||Yes||Yes|
|128-bit Hard IP Avalon-ST interface width (Hard IP only)||Yes||Yes||Yes|
|256-bit Hard IP Avalon-ST interface width (Hard IP only)||—||Yes||Yes|
|Transmitter driver electrical idle||Yes||Yes||Yes|
|8B/10B encoder/decoder disparity control||Yes||Yes||—|
|Power state management||Yes||Yes||Yes|
|Receiver PIPE status encoding ( pipe_rxstatus[2:0] )||Yes||Yes||Yes|
|Dynamic switching between 2.5 Gbps and 5 Gbps signaling rate||—||Yes||—|
|Dynamic switching between 2.5 Gbps, 5 Gbps, and 8 Gbps signaling rate||—||—||Yes|
|Dynamic transmitter margining for differential output voltage control||—||Yes||Yes|
|Dynamic transmitter buffer de-emphasis of -3.5 dB and -6 dB||—||Yes||Yes|
|Dynamic Gen3 transceiver pre-emphasis, de-emphasis, and equalization||—||—||Yes|
PIPE 2.0 Interface
In a PCIe PIPE configuration, each channel has a PIPE interface block that transfers data, control, and status signals between the PHY-MAC layer and the transceiver channel PCS and PMA blocks. The PIPE configuration complies with the PIPE 2.0 specification. If you use a PIPE configuration, you must implement the PHY-MAC layer using soft IP in the FPGA fabric.
Besides transferring data, control, and status signals between the PHY-MAC layer and the transceiver, the PIPE interface block implements the following functions required in a PCIe-compliant physical layer device:
- Forcing the transmitter driver into the electrical idle state
- Initiating the receiver detect sequence
- Controlling the 8B/10B encoder/decoder
- Controlling the 128B/130B encoder/decoder
- Managing the PCIe power states
- Indicating the completion of various PHY functions
- Encoding the receiver status and error conditions on the pipe_rxstatus[2:0] signal, conforming to the PCIe PIPE 3.0 specification
Transceiver datapath clocking varies between non-bonded (x1) and bonded (x2, x4, and x8) configurations.
Dynamic Switching Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) Signal Rates
In a PIPE configuration, the PIPE Parameter Editor provides an input signal (pipe_rate) that is functionally equivalent to the RATE signal specified in the PCIe specification. A low-to-high transition on this input signal (pipe_rate) initiates a data rate switch from Gen1 to Gen2. A high-to-low transition on the input signal initiates a data rate switch from Gen2 to Gen1. The signaling rate switch between Gen1 and Gen2 is achieved by changing the transceiver datapath clock frequency between 250 MHz and 500 MHz, while maintaining a constant, 16-bit width transceiver interface.
Transmitter Electrical Idle Generation
The PIPE interface block in Stratix V devices puts the transmitter buffer in the channel in an electrical idle state when the electrical idle input signal is asserted. During electrical idle, the transmitter buffer differential and common configuration output voltage levels are compliant to the PCIe Base Specification 2.0 for both PCIe Gen1 and Gen2 data rates.
The PCIe specification requires the transmitter driver to be in electrical idle in certain power states. For more information about input signal levels required in different power states, refer to “Power State Management”.
Power State Management
The PCIe specification defines four power states—P0, P0s, P1, and P2—that the physical layer device must support to minimize power consumption:
- P0 is the normal operating state during which packet data is transferred on the PCIe link.
- P0s, P1, and P2 are low-power states into which the physical layer must transition as directed by the PHY-MAC layer to minimize power consumption.
The PIPE interface in Stratix V transceivers provides an input port for each transceiver channel configured in a PIPE configuration.
8B/10B Encoder Usage for Compliance Pattern Transmission Support
The PCIe transmitter transmits a compliance pattern when the Link Training and Status State Machine (LTSSM) enters the Polling.Compliance substate. The Polling.Compliance substate is used to assess if the transmitter is electrically compliant with the PCIe voltage and timing specifications.
Receiver Electrical Idle Inference
The PCIe protocol allows inferring the electrical idle condition at the receiver instead of detecting the electrical idle condition with analog circuitry.
In all PIPE configurations, (x1, x2, x4, and x8), each receiver channel PCS has an optional Electrical Idle Inference module that implements the electrical idle inference conditions specified in the PCIe Base Specification 2.0.
The PCIe specification requires the PHY to encode the receiver status on a 3-bit status signal (pipe_rxstatus[2:0]). This status signal is used by the PHY-MAC layer for its operation. The PIPE interface block receives status signals from the transceiver channel PCS and PMA blocks, and encodes the status on the pipe_rxstatus[2:0] signal to the FPGA fabric. The encoding of the status signals on the pipe_rxstatus[2:0] signal conforms to the PCIe specification.
The PIPE interface block in Stratix V transceivers provides an input signal (pipe_txdetectrx_loopback) for the receiver detect operation required by the PCIe protocol during the Detect state of the LTSSM. When the pipe_txdetectrx_loopback signal is asserted in the P1 power state, the PCIe interface block sends a command signal to the transmitter driver in that channel to initiate a receiver detect sequence. In the P1 power state, the transmitter buffer must always be in the electrical idle state. After receiving this command signal, the receiver detect circuitry creates a step voltage at the output of the transmitter buffer. If an active receiver (that complies with the PCIe input impedance requirements) is present at the far end, the time constant of the step voltage on the trace is higher when compared with the time constant of the step voltage when the receiver is not present. The receiver detect circuitry monitors the time constant of the step signal seen on the trace to determine if a receiver was detected. The receiver detect circuitry requires a 125-MHz clock for operation that you must drive on the fixedclk port.
The PIPE core provides a 1-bit PHY status (pipe_phystatus) and a 3-bit receiver status signal (pipe_rxstatus[2:0]) to indicate whether a receiver was detected or not, as per the PIPE 2.0 specifications.
Gen1 and Gen2 Rate Match FIFO
In compliance with the PCIe protocol, Stratix V receiver channels have a rate match FIFO to compensate for small clock frequency differences up to ±300 ppm between the upstream transmitter and the local receiver clocks.
PCIe Reverse Parallel Loopback
PCIe reverse parallel loopback is only available in a PCIe functional configuration for Gen1, Gen2, and Gen3 data rates. The received serial data passes through the receiver CDR, deserializer, word aligner, and rate matching FIFO buffer. The data is then looped back to the transmitter serializer and transmitted out through the transmitter buffer. The received data is also available to the FPGA fabric through the port. This loopback mode is compliant with the PCIe specification 2.0. Stratix V devices provide an input signal to enable this loopback mode.
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