Stratix V Device Handbook: Volume 2: Transceivers

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ID 683779
Date 11/23/2021
Public
Document Table of Contents
Document Table of Contents x
1. Transceiver Architecture in Stratix V Devices 2. Transceiver Clocking in Stratix V Devices 3. Transceiver Reset Control in Stratix V Devices 4. Transceiver Configurations in Stratix V Devices 5. Transceiver Loopback Support in Stratix V Devices 6. Dynamic Reconfiguration in Stratix V Devices
1. Transceiver Architecture in Stratix V Devices x
1.1. Device Layout 1.2. PMA Architecture 1.3. Standard PCS Architecture 1.4. 10G PCS Architecture 1.5. PCIe Gen3 PCS Architecture 1.6. Document Revision History
1.1. Device Layout x
1.1.1. Stratix V GX/GT Channel and PCIe Hard IP Layout 1.1.2. Stratix V GS Channel and PCIe Hard IP Layout
1.1.2. Stratix V GS Channel and PCIe Hard IP Layout x
1.1.2.1. Channel Variants 1.1.2.2. GS/GT/GX Device Variants and Packages
1.2. PMA Architecture x
1.2.1. Receiver Buffer 1.2.2. Receiver Clock Data Recovery Unit 1.2.3. Receiver Deserializer 1.2.4. Transmitter PLLs 1.2.5. Transmitter Serializer 1.2.6. Transmitter Buffer 1.2.7. Transceiver Calibration Blocks 1.2.8. PMA Reconfiguration
1.2.1. Receiver Buffer x
1.2.1.1. Receiver Equalizer Gain Bandwidth 1.2.1.2. Programmable Differential On-Chip Termination (OCT) 1.2.1.3. Programmable VCM 1.2.1.4. Signal Threshold Detection Circuitry 1.2.1.5. DC Gain 1.2.1.6. Continuous Time Linear Equalization (CTLE) 1.2.1.7. Decision Feedback Equalization 1.2.1.8. EyeQ
1.2.1.8. EyeQ x
1.2.1.8.1. Serial Bit Checker
1.2.2. Receiver Clock Data Recovery Unit x
1.2.2.1. Lock-to-Reference Mode 1.2.2.2. Lock-to-Data Mode 1.2.2.3. CDR Lock Modes
1.2.2.3. CDR Lock Modes x
1.2.2.3.1. Automatic Lock Mode 1.2.2.3.2. Manual Lock Mode
1.2.3. Receiver Deserializer x
1.2.3.1. Receiver PMA Bit-Slip
1.2.4. Transmitter PLLs x
1.2.4.1. Channel PLL Used as a CMU PLL (Transmitter PLL) 1.2.4.2. Auxiliary Transmit (ATX) PLL Architecture
1.2.6. Transmitter Buffer x
1.2.6.1. Transmitter Analog Settings 1.2.6.2. Programmable Transmitter On-Chip Termination (OCT) 1.2.6.3. Link Coupling
1.2.7. Transceiver Calibration Blocks x
1.2.7.1. OCT Calibration 1.2.7.2. Offset Cancellation in the Receiver Buffer and Receiver CDR 1.2.7.3. ATX PLL Calibration 1.2.7.4. Calibration Block Boundary
1.3. Standard PCS Architecture x
1.3.1. Receiver Standard PCS Datapath 1.3.2. Transmitter Standard PCS Datapath
1.3.1. Receiver Standard PCS Datapath x
1.3.1.1. Word Aligner 1.3.1.2. PRBS Verifier 1.3.1.3. Deskew FIFO 1.3.1.4. Rate Match (Clock Rate Compensation) FIFO 1.3.1.5. 8B/10B Decoder 1.3.1.6. Byte Deserializer 1.3.1.7. Byte Ordering Block 1.3.1.8. Receiver Phase Compensation FIFO
1.3.1.8. Receiver Phase Compensation FIFO x
1.3.1.8.1. Phase Compensation Mode 1.3.1.8.2. Registered Mode
1.3.2. Transmitter Standard PCS Datapath x
1.3.2.1. Transmitter Phase Compensation FIFO 1.3.2.2. Byte Serializer 1.3.2.3. 8B/10B Encoder 1.3.2.4. PRBS Generator
1.4. 10G PCS Architecture x
1.4.1. Receiver 10G PCS Datapath 1.4.2. Transmitter 10G PCS Datapath
1.4.1. Receiver 10G PCS Datapath x
1.4.1.1. Receiver Gearbox 1.4.1.2. PRBS Verifier 1.4.1.3. Block Synchronizer 1.4.1.4. Disparity Checker 1.4.1.5. Descrambler 1.4.1.6. Frame Synchronizer 1.4.1.7. Bit-Error Rate (BER) Monitor 1.4.1.8. PRP Verifier 1.4.1.9. 64B/66B Decoder 1.4.1.10. CRC-32 Checker 1.4.1.11. Receiver FIFO
1.4.1.2. PRBS Verifier x
1.4.1.2.1. Receiver Inversion
1.4.2. Transmitter 10G PCS Datapath x
1.4.2.1. Transmitter FIFO 1.4.2.2. Frame Generator 1.4.2.3. CRC-32 Generator 1.4.2.4. 64B/66B Encoder 1.4.2.5. Scrambler 1.4.2.6. Disparity Generator 1.4.2.7. PRBS Generator 1.4.2.8. Transmitter Gearbox
1.4.2.5. Scrambler x
1.4.2.5.1. PRP Generator
1.4.2.7. PRBS Generator x
1.4.2.7.1. Transmitter Inversion
1.5. PCIe Gen3 PCS Architecture x
1.5.1. Receiver PCIe Gen3 PCS Datapath 1.5.2. Transmitter PCIe Gen3 PCS Datapath 1.5.3. PIPE Interface
1.5.1. Receiver PCIe Gen3 PCS Datapath x
1.5.1.1. Block Synchronizer 1.5.1.2. Rate Match FIFO 1.5.1.3. Decoder 1.5.1.4. Descrambler 1.5.1.5. Receiver Phase Compensation FIFO
1.5.2. Transmitter PCIe Gen3 PCS Datapath x
1.5.2.1. Transmitter Phase Compensation FIFO 1.5.2.2. Scrambler 1.5.2.3. Encoder 1.5.2.4. Gearbox
1.5.3. PIPE Interface x
1.5.3.1. Auto Speed Negotiation 1.5.3.2. Electrical Idle Inference 1.5.3.3. Clock Data Recovery (CDR) Control
2. Transceiver Clocking in Stratix V Devices x
2.1. Input Reference Clocking 2.2. Internal Clocking 2.3. FPGA Fabric-Transceiver Interface Clocking 2.4. Document Revision History
2.1. Input Reference Clocking x
2.1.1. Input Reference Clock Sources
2.1.1. Input Reference Clock Sources x
2.1.1.1. Dedicated refclk Pins 2.1.1.2. Dedicated refclk Pins Using the Reference Clock Network 2.1.1.3. RX Pins Using the Reference Clock Network 2.1.1.4. Fractional PLLs
2.2. Internal Clocking x
2.2.1. Transmitter Clock Network 2.2.2. Transmitter Clocking 2.2.3. Receiver Clocking
2.2.1. Transmitter Clock Network x
2.2.1.1. Transmitter Clock Lines 2.2.1.2. Clock Dividers 2.2.1.3. Transmitter Clock Network in Stratix V GT Transceiver Channels
2.2.2. Transmitter Clocking x
2.2.2.1. Transmitter 10G PCS Clocking 2.2.2.2. Transmitter Standard PCS Clocking 2.2.2.3. Transmitter GT Channel Clocking
2.2.2.2. Transmitter Standard PCS Clocking x
2.2.2.2.1. Non-Bonded Channel Configurations Using the x1 Clock Network 2.2.2.2.2. Non-Bonded Channel Configurations Using the xN Clock Network 2.2.2.2.3. Bonded Channel Configurations 2.2.2.2.4. Bonded Channel Configurations Using the xN Clock Network 2.2.2.2.5. Bonded Channel Configurations Using the PLL Feedback Compensation Path
2.2.3. Receiver Clocking x
2.2.3.1. GX Channel Receiver Clocking 2.2.3.2. GT Channel Receiver Clocking
2.2.3.1. GX Channel Receiver Clocking x
2.2.3.1.1. Non-Bonded Channel Configurations 2.2.3.1.2. Bonded Channel Configurations
2.3. FPGA Fabric-Transceiver Interface Clocking x
2.3.1. Transmitter Datapath Interface Clocking 2.3.2. Receiver Datapath Interface Clock 2.3.3. GXB 0 PPM Core Clock Assignment
2.3.1. Transmitter Datapath Interface Clocking x
2.3.1.1. Quartus II-Selected Transmitter Datapath Interface Clock 2.3.1.2. Selecting a Transmitter Datapath Interface Clock
2.3.2. Receiver Datapath Interface Clock x
2.3.2.1. Quartus II Software-Selected Receiver Datapath Interface Clock 2.3.2.2. Selecting a Receiver Datapath Interface Clock
3. Transceiver Reset Control in Stratix V Devices x
3.1. PHY IP Embedded Reset Controller 3.2. User-Coded Reset Controller 3.3. Transceiver Reset Using Avalon Memory Map Registers 3.4. Clock Data Recovery in Manual Lock Mode 3.5. Transceiver Blocks Affected by the Reset and Powerdown Signals 3.6. Document Revision History
3.1. PHY IP Embedded Reset Controller x
3.1.1. Embedded Reset Controller Signals 3.1.2. Resetting the Transceiver with the PHY IP Embedded Reset Controller During Device Power-Up 3.1.3. Resetting the Transceiver with the PHY IP Embedded Reset Controller During Device Operation
3.2. User-Coded Reset Controller x
3.2.1. User-Coded Reset Controller Signals 3.2.2. Resetting the Transmitter with the User-Coded Reset Controller During Device Power-Up 3.2.3. Resetting the Transmitter with the User-Coded Reset Controller During Device Operation 3.2.4. Resetting the Receiver with the User-Coded Reset Controller During Device Power-Up Configuration 3.2.5. Resetting the Receiver with the User-Coded Reset Controller During Device Operation
3.3. Transceiver Reset Using Avalon Memory Map Registers x
3.3.1. Transceiver Reset Control Signals Using Avalon Memory Map Registers
3.4. Clock Data Recovery in Manual Lock Mode x
3.4.1. Control Settings for CDR Manual Lock Mode 3.4.2. Resetting the Transceiver in CDR Manual Lock Mode
4. Transceiver Configurations in Stratix V Devices x
4.1. Protocols and Transceiver PHY IP Support 4.2. 10GBASE-R and 10GBASE-KR 4.3. Interlaken 4.4. PCI Express (PCIe)—Gen1, Gen2, and Gen3 4.5. XAUI 4.6. CPRI and OBSAI—Deterministic Latency Protocols 4.7. Transceiver Configurations 4.8. Native PHY IP Configuration 4.9. Stratix V GT Device Configurations 4.10. Document Revision History
4.2. 10GBASE-R and 10GBASE-KR x
4.2.1. 10GBASE-R and 10GBASE-KR Transceiver Datapath Configuration 4.2.2. 10GBASE-R and 10GBASE-KR Supported Features 4.2.3. 1000BASE-X and 1000BASE-KX Transceiver Datapath 4.2.4. 1000BASE-X and 1000BASE-KX Supported Features 4.2.5. Synchronization State Machine Parameters in 1000BASE-X and 1000BASE-KX Configurations 4.2.6. Transceiver Clocking in 10GBASE-R, 10GBASE-KR, 1000BASE-X, and 1000BASE-KX Configurations
4.3. Interlaken x
4.3.1. Transceiver Datapath Configuration 4.3.2. Supported Features 4.3.3. Transceiver Clocking
4.4. PCI Express (PCIe)—Gen1, Gen2, and Gen3 x
4.4.1. Transceiver Datapath Configuration 4.4.2. Supported Features for PCIe Configurations PIPE 2.0 Interface Dynamic Switching Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) Signal Rates Transmitter Electrical Idle Generation Power State Management 8B/10B Encoder Usage for Compliance Pattern Transmission Support Receiver Electrical Idle Inference Receiver Status Receiver Detection Gen1 and Gen2 Rate Match FIFO PCIe Reverse Parallel Loopback 4.4.3. Supported Features for PCIe Gen3 4.4.4. Transceiver Clocking and Channel Placement Guidelines 4.4.5. Advanced Channel Placement Guidelines for PIPE Configurations 4.4.6. Transceiver Clocking for PCIe Gen3
4.5. XAUI x
4.5.1. Transceiver Datapath in a XAUI Configuration 4.5.2. Supported Features 4.5.3. Transceiver Clocking and Channel Placement Guidelines
4.6. CPRI and OBSAI—Deterministic Latency Protocols x
4.6.1. Transceiver Datapath Configuration 4.6.2. Phase Compensation FIFO in Register Mode 4.6.3. Channel PLL Feedback 4.6.4. CPRI and OBSAI 4.6.5. CPRI Enhancements
4.7. Transceiver Configurations x
4.7.1. Standard PCS Configurations—Custom Datapath 4.7.2. Standard PCS Configurations—Low Latency Datapath 4.7.3. Transceiver Channel Placement Guidelines 4.7.4. 10G PCS Configurations 4.7.5. Merging Instances
4.7.4. 10G PCS Configurations x
4.7.4.1. 10G PCS Datapath Functionality 4.7.4.2. Using the coreclkin Ports
4.8. Native PHY IP Configuration x
4.8.1. Native PHY Transceiver Datapath Configuration 4.8.2. Standard PCS Features 4.8.3. 10G PCS Supported Features 4.8.4. 10G Datapath Configurations with Native PHY IP 4.8.5. PMA Direct Supported Features 4.8.6. Channel and PCS Datapath Dynamic Switching Reconfiguration
4.8.2. Standard PCS Features x
4.8.2.1. Standard PCS Receiver and Transmitter Blocks
4.8.3. 10G PCS Supported Features x
4.8.3.1. 10G PCS Receiver and Transmitter Blocks 4.8.3.2. Receiver and Transmit Gearbox in Native PHY IP
5. Transceiver Loopback Support in Stratix V Devices x
5.1. Serial Loopback 5.2. PIPE Reverse Parallel Loopback 5.3. Reverse Serial Loopback 5.4. Reverse Serial Pre-CDR Loopback 5.5. Document Revision History
6. Dynamic Reconfiguration in Stratix V Devices x
6.1. Dynamic Reconfiguration Features 6.2. Offset Cancellation 6.3. PMA Analog Controls Reconfiguration 6.4. On-Chip Signal Quality Monitoring (Eye Viewer) 6.5. Decision Feedback Equalization 6.6. Adaptive Equalization 6.7. Dynamic Reconfiguration of Loopback Modes 6.8. Transceiver PLL Reconfiguration 6.9. Transceiver Channel Reconfiguration 6.10. Transceiver Interface Reconfiguration 6.11. Document Revision History
1. Transceiver Architecture in Stratix V Devices
2. Transceiver Clocking in Stratix V Devices
3. Transceiver Reset Control in Stratix V Devices
4. Transceiver Configurations in Stratix V Devices
5. Transceiver Loopback Support in Stratix V Devices
6. Dynamic Reconfiguration in Stratix V Devices

4.4.2. Supported Features for PCIe Configurations

The features supported for a PCIe configuration are different for the 2.5 Gbps, 5 Gbps, and 8 Gbps data rate configurations.
Table 35.  Supported Features for PCIe Configurations
Feature

Gen1

(2.5 Gbps)

Gen2

(5 Gbps)

Gen3

(8 Gbps)

x1, x2, x4, x8 link configurations Yes Yes Yes
PCIe-compliant synchronization state machine Yes Yes Yes
±300 ppm (total 600 ppm) clock rate compensation Yes Yes Yes
8-bit FPGA fabric-transceiver interface (PIPE 2.0) Yes — —
16-bit FPGA fabric-transceiver interface (PIPE 2.0) Yes Yes —
32-bit FPGA fabric-transceiver interface (PIPE 3.0-like) — — Yes
64-bit Hard IP Avalon-ST interface width (Hard IP only) Yes Yes Yes
128-bit Hard IP Avalon-ST interface width (Hard IP only) Yes Yes Yes
256-bit Hard IP Avalon-ST interface width (Hard IP only) — Yes Yes
Transmitter driver electrical idle Yes Yes Yes
Receiver Detection Yes Yes Yes
8B/10B encoder/decoder disparity control Yes Yes —
128B/130B encoder/decoder — — Yes
Power state management Yes Yes Yes
Receiver PIPE status encoding ( pipe_rxstatus[2:0] ) Yes Yes Yes
Dynamic switching between 2.5 Gbps and 5 Gbps signaling rate — Yes —
Dynamic switching between 2.5 Gbps, 5 Gbps, and 8 Gbps signaling rate — — Yes
Dynamic transmitter margining for differential output voltage control — Yes Yes
Dynamic transmitter buffer de-emphasis of -3.5 dB and -6 dB — Yes Yes
Dynamic Gen3 transceiver pre-emphasis, de-emphasis, and equalization — — Yes

PIPE 2.0 Interface

In a PCIe PIPE configuration, each channel has a PIPE interface block that transfers data, control, and status signals between the PHY-MAC layer and the transceiver channel PCS and PMA blocks. The PIPE configuration complies with the PIPE 2.0 specification. If you use a PIPE configuration, you must implement the PHY-MAC layer using soft IP in the FPGA fabric.

Besides transferring data, control, and status signals between the PHY-MAC layer and the transceiver, the PIPE interface block implements the following functions required in a PCIe-compliant physical layer device:

  • Forcing the transmitter driver into the electrical idle state
  • Initiating the receiver detect sequence
  • Controlling the 8B/10B encoder/decoder
  • Controlling the 128B/130B encoder/decoder
  • Managing the PCIe power states
  • Indicating the completion of various PHY functions
  • Encoding the receiver status and error conditions on the pipe_rxstatus[2:0] signal, conforming to the PCIe PIPE 3.0 specification

Transceiver datapath clocking varies between non-bonded (x1) and bonded (x2, x4, and x8) configurations.

Dynamic Switching Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) Signal Rates

In a PIPE configuration, the PIPE Parameter Editor provides an input signal (pipe_rate) that is functionally equivalent to the RATE signal specified in the PCIe specification. A low-to-high transition on this input signal (pipe_rate) initiates a data rate switch from Gen1 to Gen2. A high-to-low transition on the input signal initiates a data rate switch from Gen2 to Gen1. The signaling rate switch between Gen1 and Gen2 is achieved by changing the transceiver datapath clock frequency between 250 MHz and 500 MHz, while maintaining a constant, 16-bit width transceiver interface.

Transmitter Electrical Idle Generation

The PIPE interface block in Stratix V devices puts the transmitter buffer in the channel in an electrical idle state when the electrical idle input signal is asserted. During electrical idle, the transmitter buffer differential and common configuration output voltage levels are compliant to the PCIe Base Specification 2.0 for both PCIe Gen1 and Gen2 data rates.

The PCIe specification requires the transmitter driver to be in electrical idle in certain power states. For more information about input signal levels required in different power states, refer to “Power State Management”.

Power State Management

The PCIe specification defines four power states—P0, P0s, P1, and P2—that the physical layer device must support to minimize power consumption:

  • P0 is the normal operating state during which packet data is transferred on the PCIe link.
  • P0s, P1, and P2 are low-power states into which the physical layer must transition as directed by the PHY-MAC layer to minimize power consumption.

The PIPE interface in Stratix V transceivers provides an input port for each transceiver channel configured in a PIPE configuration.

Note: When transitioning from the P0 power state to lower power states (P0s, P1, and P2), the PCIe specification requires the physical layer device to implement power saving measures. Stratix V transceivers do not implement these power saving measures except for putting the transmitter buffer in electrical idle in the lower power states.

8B/10B Encoder Usage for Compliance Pattern Transmission Support

The PCIe transmitter transmits a compliance pattern when the Link Training and Status State Machine (LTSSM) enters the Polling.Compliance substate. The Polling.Compliance substate is used to assess if the transmitter is electrically compliant with the PCIe voltage and timing specifications.

Receiver Electrical Idle Inference

The PCIe protocol allows inferring the electrical idle condition at the receiver instead of detecting the electrical idle condition with analog circuitry.

In all PIPE configurations, (x1, x2, x4, and x8), each receiver channel PCS has an optional Electrical Idle Inference module that implements the electrical idle inference conditions specified in the PCIe Base Specification 2.0.

Receiver Status

The PCIe specification requires the PHY to encode the receiver status on a 3-bit status signal (pipe_rxstatus[2:0]). This status signal is used by the PHY-MAC layer for its operation. The PIPE interface block receives status signals from the transceiver channel PCS and PMA blocks, and encodes the status on the pipe_rxstatus[2:0] signal to the FPGA fabric. The encoding of the status signals on the pipe_rxstatus[2:0] signal conforms to the PCIe specification.

Receiver Detection

The PIPE interface block in Stratix V transceivers provides an input signal (pipe_txdetectrx_loopback) for the receiver detect operation required by the PCIe protocol during the Detect state of the LTSSM. When the pipe_txdetectrx_loopback signal is asserted in the P1 power state, the PCIe interface block sends a command signal to the transmitter driver in that channel to initiate a receiver detect sequence. In the P1 power state, the transmitter buffer must always be in the electrical idle state. After receiving this command signal, the receiver detect circuitry creates a step voltage at the output of the transmitter buffer. If an active receiver (that complies with the PCIe input impedance requirements) is present at the far end, the time constant of the step voltage on the trace is higher when compared with the time constant of the step voltage when the receiver is not present. The receiver detect circuitry monitors the time constant of the step signal seen on the trace to determine if a receiver was detected. The receiver detect circuitry requires a 125-MHz clock for operation that you must drive on the fixedclk port.

Note: For the receiver detect circuitry to function reliably, the transceiver on-chip termination must be used and the AC-coupling capacitor on the serial link and the receiver termination values used in your system must be compliant with the PCIe Base Specification 2.0.

The PIPE core provides a 1-bit PHY status (pipe_phystatus) and a 3-bit receiver status signal (pipe_rxstatus[2:0]) to indicate whether a receiver was detected or not, as per the PIPE 2.0 specifications.

Gen1 and Gen2 Rate Match FIFO

In compliance with the PCIe protocol, Stratix V receiver channels have a rate match FIFO to compensate for small clock frequency differences up to ±300 ppm between the upstream transmitter and the local receiver clocks.

PCIe Reverse Parallel Loopback

PCIe reverse parallel loopback is only available in a PCIe functional configuration for Gen1, Gen2, and Gen3 data rates. The received serial data passes through the receiver CDR, deserializer, word aligner, and rate matching FIFO buffer. The data is then looped back to the transmitter serializer and transmitted out through the transmitter buffer. The received data is also available to the FPGA fabric through the port. This loopback mode is compliant with the PCIe specification 2.0. Stratix V devices provide an input signal to enable this loopback mode.

Note: This is the only loopback option supported in PIPE configurations.
Figure 105. PCIe Reverse Parallel Loopback Mode DatapathThe grayed-out blocks are Inactive.


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