Stratix V Device Handbook: Volume 2: Transceivers

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ID 683779
Date 11/23/2021
Public
Document Table of Contents

2.3.2.2. Selecting a Receiver Datapath Interface Clock

Multiple non-bonded receiver channels use a large portion of GCLK, RCLK, and PCLK resources. Selecting a common clock driver for the receiver datapath interface of all identical receiver channels saves clock resources.
Non-bonded multiple receiver channels lead to high utilization of GCLK, RCLK, and PCLK resources—one clock resource per channel. You can significantly reduce GCLK, RCLK, and PCLK resource use for the receiver datapath clocks if the receiver channels are identical.
Note: Identical receiver channels are defined as channels that have the same input reference clock source for the CDR and the same receiver PMA and PCS configuration. Identical receiver channels need to be PPM aligned with regards to their remote transmitters. These channels may have different analog settings, such as receiver common mode voltage (VICM), equalization, or DC gain setting.

To achieve clock resource savings, select a common clock driver for the receiver datapath interface of all identical receiver channels. To select a common clock driver, perform these steps:

  1. Instantiate the rx_coreclkin port for all the identical receiver channels.
  2. Connect the common clock driver to their receiver datapath interface, and receiver data and control logic.
The following figure shows eight identical channels that are clocked by a single clock (rx_clkout of channel 4).
Figure 76. Eight Identical Channels with a Single User-Selected Receiver Interface Clock


To clock eight identical channels with a single clock, perform these steps:

  • Instantiate the rx_coreclkin port for all the identical receiver channels (rx_coreclkin[7:0]).
  • Connect rx_clkout[4] to the rx_coreclkin[7:0] ports.
  • Connect rx_clkout[4] to the receiver data and control logic for all eight channels.
Note: Resetting or powering down channel 4 leads to a loss of the clock for all eight channels.

The common clock must have a 0 ppm difference for the write side of the RX phase compensation FIFO of all the identical channels. A frequency difference causes the FIFO to under run or overflow, depending on whether the common clock is faster or slower, respectively.

You can drive the 0 ppm common clock driver from one of the following sources:

  • tx_clkout of any channel in non-bonded receiver channel configurations with the rate matcher
  • rx_clkout of any channel in non-bonded receiver channel configurations without the rate matcher
  • tx_clkout[0] in bonded receiver channel configurations
  • Dedicated refclk pins
Note: The Quartus II software does not allow gated clocks or clocks generated in the FPGA logic to drive the rx_coreclkin ports.
Note: You must ensure a 0 ppm difference. The Quartus II software is unable to ensure a 0 ppm difference because it allows you to use external pins, such as dedicated refclk pins.

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