184.108.40.206. Selecting a Receiver Datapath Interface Clock
To achieve clock resource savings, select a common clock driver for the receiver datapath interface of all identical receiver channels. To select a common clock driver, perform these steps:
- Instantiate the rx_coreclkin port for all the identical receiver channels.
- Connect the common clock driver to their receiver datapath interface, and receiver data and control logic.
To clock eight identical channels with a single clock, perform these steps:
- Instantiate the rx_coreclkin port for all the identical receiver channels (rx_coreclkin[7:0]).
- Connect rx_clkout to the rx_coreclkin[7:0] ports.
- Connect rx_clkout to the receiver data and control logic for all eight channels.
The common clock must have a 0 ppm difference for the write side of the RX phase compensation FIFO of all the identical channels. A frequency difference causes the FIFO to under run or overflow, depending on whether the common clock is faster or slower, respectively.
You can drive the 0 ppm common clock driver from one of the following sources:
- tx_clkout of any channel in non-bonded receiver channel configurations with the rate matcher
- rx_clkout of any channel in non-bonded receiver channel configurations without the rate matcher
- tx_clkout in bonded receiver channel configurations
- Dedicated refclk pins
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