Stratix V Device Handbook: Volume 2: Transceivers

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ID 683779
Date 11/23/2021
Public
Document Table of Contents

1. Transceiver Architecture in Stratix V Devices

For a complete understanding of Stratix® V transceivers, first review the transceiver architecture chapter, then refer to the subsequent chapters in this volume.

You can implement Stratix® V transceivers using Altera's transceiver intellectual property (IP) which are part of the Quartus® II software.

Stratix® V devices provide up to 66 backplane-capable full-duplex clock data recovery (CDR)–based transceivers.

Table 1.  Device Variants
Stratix Device Channel Type
GX GT
GS 600 Mbps to 14.1 Gbps Not supported
GX 600 Mbps to 14.1 Gbps Not supported
GT 600 Mbps to 12.5 Gbps 19.6 Gbps to 28.05 Gbps

Stratix® V transceivers are divided into two blocks: physical medium attachment (PMA) and physical coding sublayer (PCS). The PMA block connects the FPGA to the channel, generates the required clocks, and converts the data from parallel to serial or serial to parallel. The PCS block performs digital processing logic between the PMA and the FPGA core. The PCS block contains the digital processing interface between the PMA and FPGA core. There are three types of PCS blocks in Stratix® V devices: a standard PCS block, a 10G PCS, and a PCIe Gen3 PCS that supports the PCIe Gen3 Base specification.

Stratix V transceivers are structured into full-duplex (transmitter and receiver) six-channel groups called transceiver blocks.

Figure 1. Single Full-Duplex GX Channel
Figure 2. Single Full-Duplex GT ChannelThe GT channels do not have PCS.

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