Visible to Intel only — GUID: nik1409773831962
Ixiasoft
Visible to Intel only — GUID: nik1409773831962
Ixiasoft
1.5.2.2. Scrambler
In a multi-lane link environment, each of the transmitter lanes may implement a LFSR for scrambling. The LFSR uses the following polynomial: G(X) = X23 + X21 + X16 + X8 + X5 +X2 + 1. It is a standard PRBS23 polynomial. The scrambler is used to provide enough edge density, since there is no 8B/10B encoding in PCIe Gen3, so that the RX PMA CDR can lock to the incoming data stream and generate the recovered clock.
Did you find the information on this page useful?
Feedback Message
Characters remaining: