Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

2.1.1. Input Reference Clock Sources

The channel PLL, ATX PLL, and fractional PLL can derive the input clock from a dedicated refclk pin, another fractional PLL, or through the reference clock network.
Figure 44. Input Reference Clock Sources to Transmit PLLs and CDR


Note: For optimal performance, use the refclk source that is closest to the transmit PLL in the same transceiver bank.
In order to use a fractional PLL to provide the reference clock to the transceiver channel the following conditions must be satisfied:
  1. The fractional PLL must be in the PLL strip on the same side as the transceiver channel.
  2. The counter output that feeds the transceiver channel cannot drive logic in the fabric.
Figure 45. Input Reference Clock Sources for GX Transceiver ChannelsFor more information about the fractional PLL input clock sources shown in the following figure, refer to .


The following figure shows the input reference clock sources for a GT transceiver channel and two GX transceiver channels in a GT transceiver bank.

Figure 46. Input Reference Clock Sources for GT and GX Transceiver Channels in Stratix V GT DevicesFor more information about the fractional PLL input clock sources shown in the following figure, refer to .


Note: Altera recommends using a dedicated clock refclk0 for the bottom ATX PLL that provides the serial clock to the GT transmitter channel.

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