Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

2.3.1. Transmitter Datapath Interface Clocking

The transmitter datapath interface consists of the following:
  • Write side of the TX phase compensation FIFO—for configurations that use the standard PCS channel
  • Write side of the TX FIFO—for configurations that use the 10G PCS channel

This interface is clocked by the transmitter datapath interface clock. The transmitter PCS forwards the following clocks to the FPGA fabric:

  • tx_clkout for each transmitter channel in non-bonded configuration
  • tx_clkout[0] for all transmitter channels in bonded configuration
Figure 70. Transmitter Datapath Interface Clocking


All configurations using the standard PCS channel must have a 0 parts per million (ppm) difference between the transmitter datapath interface clock and the read side clock of the TX phase compensation FIFO.

Note: For more information about interface clocking for each configuration, refer to the Transceiver Configurations in Stratix V Devices chapter.

You can clock the transmitter datapath interface by using one of the following:

  • Quartus II-selected transmitter datapath interface clock
  • User-selected transmitter datapath interface clock
Note: User selection allows you to share the transceiver datapath interface clocks to reduce GCLK, RCLK, and PCLK resource utilization in your design.

Did you find the information on this page useful?

Characters remaining:

Feedback Message