2.3.1. Transmitter Datapath Interface Clocking
- Write side of the TX phase compensation FIFO—for configurations that use the standard PCS channel
- Write side of the TX FIFO—for configurations that use the 10G PCS channel
This interface is clocked by the transmitter datapath interface clock. The transmitter PCS forwards the following clocks to the FPGA fabric:
- tx_clkout for each transmitter channel in non-bonded configuration
- tx_clkout for all transmitter channels in bonded configuration
All configurations using the standard PCS channel must have a 0 parts per million (ppm) difference between the transmitter datapath interface clock and the read side clock of the TX phase compensation FIFO.
You can clock the transmitter datapath interface by using one of the following:
- Quartus II-selected transmitter datapath interface clock
- User-selected transmitter datapath interface clock
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