Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

3.2. User-Coded Reset Controller

You must implement external reset controller logic (user-coded reset controller) if you disable the embedded reset controller to initialize the transceiver physical coding sublayer (PCS) and physical medium attachment (PMA) blocks.

You can implement a user-coded reset controller with one of the following:

  • Using your own Verilog/VHDL code to implement the reset sequence
  • Using the Quartus II IP Catalog, which provides a ready-made reset controller IP to place your own Verilog/VHDL code

When using manual mode, you must create a user-coded reset controller to manage the input signals.

Note: You must disable the embedded reset controller before using the user-coded reset controller.
Note: The embedded reset controller can only be disabled for non-protocol transceiver PHY IPs, such as 10GBASE-R PHY, custom PHY, low latency PHY and deterministic latency PHY. Native PHY IP does not have an embedded reset controller, so you must implement your own reset logic.
Note: If you do not follow the Stratix V power sequence, you might encounter transceiver functionality issues, especially with regard to the pll_locked signal.

If you implement your own reset controller, consider the following:

  • The user-coded reset controller must be level sensitive (active high)
  • The user-coded reset controller does not depend on phy_mgmt_clk_reset
  • You must provide a clock and reset to the reset controller logic
  • The internal signals of the PHY IP embedded reset controller are configured as ports
  • You can hold the transceiver channels in reset by asserting the appropriate reset control signals
Note:

You must have a valid and stable ATX PLL reference clock before deasserting the pll_powerdown and mgmt_rst_reset signals for successful ATX PLL calibration.

This reset controller comes with a clear text Verilog file that you modify based on your requirements.

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