3.2. User-Coded Reset Controller
You can implement a user-coded reset controller with one of the following:
- Using your own Verilog/VHDL code to implement the reset sequence
- Using the Quartus II IP Catalog, which provides a ready-made reset controller IP to place your own Verilog/VHDL code
When using manual mode, you must create a user-coded reset controller to manage the input signals.
If you implement your own reset controller, consider the following:
- The user-coded reset controller must be level sensitive (active high)
- The user-coded reset controller does not depend on phy_mgmt_clk_reset
- You must provide a clock and reset to the reset controller logic
- The internal signals of the PHY IP embedded reset controller are configured as ports
- You can hold the transceiver channels in reset by asserting the appropriate reset control signals
You must have a valid and stable ATX PLL reference clock before deasserting the pll_powerdown and mgmt_rst_reset signals for successful ATX PLL calibration.
This reset controller comes with a clear text Verilog file that you modify based on your requirements.
Did you find the information on this page useful?