Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

2.3.1.1. Quartus II-Selected Transmitter Datapath Interface Clock

The Quartus II software automatically picks the appropriate clock from the FPGA fabric to clock the transmitter datapath interface.
Figure 71.  Transmitter Datapath Interface Clocking for Non-Bonded ChannelsThe figure shows the transmitter datapath interface of two non-bonded channels clocked by their respective transmitter PCS clocks that are forwarded to the FPGA fabric.


Note: The FPGA fabric-transceiver interface clocking for GT transmitter channels is similar to the non-bonded GX transmitter channel FPGA fabric-transceiver interface clocking.
Figure 72. Transmitter Datapath Interface Clocking for Three Bonded ChannelsThe figure shows the transmitter datapath interface of three bonded channels clocked by the tx_clkout[0] clock. The tx_clkout clock is derived from the central clock divider of channel 1 or 4 in a transceiver bank.


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