Stratix V Device Handbook: Volume 2: Transceivers

Download
ID 683779
Date 11/23/2021
Public
Document Table of Contents

1.6. Document Revision History

The revision history for this chapter.
Table 14.  Document Revision History
Date Version Changes
January 2016 2016.01.11 Made the following changes:
  • Added a note to the "Receiver FIFO" section.
  • Added a note to the "Transmitter FIFO" section.
September 2014 2014.09.30
  • Added a link to Altera mySupport in the Link Coupling section.
  • Added a note to the 10G PCS Datapath in Stratix V GX Channels figure.
  • Added a note to the Rate Match (Clock Compensation) FIFO section.
  • Added the "Word Aligner in Deterministic Latency State Machine Mode" section and updated the Manual Mode description in the Word Aligner section.
  • Removed the values for Word Alignment Pattern Length in Bit-Slip mode in the Word Aligner Options table.
  • Removed XAUI Mode and PCIe Mode from the Receiver Phase Compensation FIFO section.
  • Added the following columns to the Transceiver Calibration Block Boundary for Stratix V Devices table:
    • Package
    • Total Number of Transceiver channels in device
    • Total Number of Transceiver Channels per Side
  • Changed the description of the receiver phase compensation FIFO.
  • Added the Phase Compensation Mode section.
  • Added the Registered Mode section.
  • Added the Receiver Inversion section.
  • Added the Transmitter Inversion section.
  • Changed "MegaWizard Plug-in Manager" to "IP catalog" in the 10G PCS Architecture section.
  • Updated the PCIe Gen3 PCS Top Level Block Diagram to show the pld_rx_clk as an input to the Phase Compensation FIFO block.
January 2014 2014.01.07
  • Updated the Stratix V GX/GT Channel and PCIe Hard IP Layout section.
  • Updated the Stratix V GS Channel and PCIe Hard IP Layout section.
  • Updated the Channel Variants section.
  • Updated the GS/GT/GX Device Variants and Packages section.
  • Updated the Receiver Equalizer Gain Bandwidth section.
October 2013 2013.10.11
  • Updated the Word Aligner section.
  • Updated the Lock-to-Reference Mode section.
May 2013 2013.05.06
  • Added link to the known document issues in the Knowledge Base
  • Updated Figure 1-10.
  • Updated Figure 1-15.
  • Updated the Receiver Deserializer section.
  • Updated the Continuous Time Linear Equalization section.
  • Added the GS/GT/GX Device Variants and Packages section.
  • Added the Stratix V GS Channel and PCIe Hard IP Layout section.
  • Updated Figure 1-17.
  • Updated Figure 1-18.
  • Updated Figure 1-30.
  • Added the PRBS Verifier section.
  • Added the PRBS Generator section.
  • Added the PRP Verifier section.
  • Added the Serial Bit Checker section.
  • Updated the Decision Feedback Equalization section.
  • Updated the Transmitter Analog Settings section.
  • Updated the Receiver PMA Bit-Slip section.
  • Updated the ATX PLL Calibration section.
  • Updated the Calibration Block Boundary section.
  • Updated Figure 1-20.
  • Updated the 8B/10B Decoder section.
  • Updated the Transmitter Phase Compensation FIFO section.
December 2012 2012.12.17 Reorganized content and updated template .
June 2012 2.3
  • Updated Figure 1–6, Figure 1–10, and Figure 1–11.
  • Updated Table 1–3
  • Updated “Stratix V Device Layout”, “PMA Architecture”, “Standard PCS Architecture” and “10G PCS Architecture” sections.
  • Updated Table 1–2, Table 1–4, Table 1–1, and Table 1–5.
  • Updated Figure 1–1, Figure 1–3, Figure 1–4, Figure 1–8, and Figure 1–21.
  • Updated “Transmitter Polarity Inversion” section.
  • Added “PCIe Gen3 PCS Architecture” section.
February 2012 2.2
  • Updated Figure 1–1.
  • Updated “Transmitter Polarity Inversion” section.

Did you find the information on this page useful?

Characters remaining:

Feedback Message