1.3. Standard PCS Architecture
The transceiver Standard PCS circuit blocks support data rates up to 12.2 Gbps depending on the transceiver speed grade.
Some transceiver channels interface to the PCIe hard IP block, the PIPE interface for soft IP implementations of PCIe, or directly to the FPGA fabric (FPGA fabric-transceiver interface). The transceiver channel interfaces to the PCIe hard IP block if you use the hard IP block to implement the PCIe PHY MAC, data link layer, and transaction layer. Otherwise, the transceiver channel interfaces directly to the FPGA fabric.
The PCIe hard IP-transceiver interface is outside the scope of this chapter. This chapter describes the FPGA fabric-transceiver interface only.
You can divide the standard transceiver channel datapath into two configurations based on the FPGA fabric-transceiver interface width (channel width) and the transceiver channel PMA-PCS width (serialization factor).
|Name||8- and 10-Bit PMA-PCS Widths||16- and 20-Bit PMA-PCS Widths|
|FPGA fabric-transceiver interface widths||
8 and 10 bit
16 and 20 bit
16 and 20 bit
32 and 40 bit
PCIe Gen1 and Gen2
Custom configuration (Custom or Native or Low Latency PHY IPs)
|Custom configuration (Custom or Native or Low Latency PHY IPs)|
|Data rate range in a custom configuration||0.6 to 3.75 Gbps||1.0 to 12.2 Gbps|
The standard PCS can be configured for various protocols by selecting different PCS blocks in the receiver and transmitter datapath.
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