Stratix V Device Handbook: Volume 2: Transceivers

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ID 683779
Date 11/23/2021
Public
Document Table of Contents

2.1.1.1. Dedicated refclk Pins

GX transceiver banks have one dedicated refclk pin for each group of three transceiver channels. The dedicated refclk0/refclk1 pins can drive reference clock network or ch1/ch4 channel PLLs respectively in a transceiver bank.

There are two dedicated refclk pins available in each GT transceiver bank. The two refclk pins can also provide the reference clocks to the GX channels in a GT transceiver bank through the reference clock network.

Power pins associated with transceiver banks must be powered up. At least one transceiver must be instantiated in the design if a dedicated transceiver refclk pin is used as a clock reference for a core fPLL.

The following table lists the electrical specifications for the input reference clock signal driven on the refclk pins.

Table 15.  Electrical Specifications for the Input Reference Clock
Protocol I/O Standard Coupling Termination
PCI Express (PCIe)
  • 1.2V PCML, 1.4 PCML
  • 1.4V PCML
  • 1.5V PCML
  • 2.5V PCML
  • Differential LVPECL
  • LVDS
AC On - Chip 1
  • HCSL 2
DC Off - Chip 3
All other protocols
  • 1.2V PCML, 1.4 PCML
  • 1.4V PCML
  • 1.5V PCML
  • 2.5V PCML
  • Differential LVPECL
  • LVDS
AC On - Chip 1
Note: If you select the HCSL I/O standard for the PCIe reference clock, add the following assignment to your project's quartus settings file (.qsf):
set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION_DC_COUPLING_EXTERNAL_RESISTOR -to <refclk_pin_name>
Figure 47. Termination Scheme for a Reference Clock Signal When Configured as HCSL


Note:
  1. No biasing is required if the reference clock signals are generated from a clock source that conforms to the PCIe specification
  2. Select Rs and / or Rp resistor values as recommended by the PCIe clock source vendor.
1 For more information about termination values supported, refer to the DC Characteristics section in Stratix V Device Datasheet.
2 In PCIe mode, you have the option of selecting the HCSL standard for the reference clock if compliance to the PCIe protocol is required. You can select this I/O standard option only if you have configured the transceiver in PCIe mode.
3 For an example termination scheme, refer to Figure 47

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