Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Document Table of Contents

4.5.3. Transceiver Clocking and Channel Placement Guidelines

Transceiver Clocking

Figure 131. Transceiver Clocking Diagram for XAUI ConfigurationOne of the two channel PLLs configured as a CMU PLL in a transceiver bank generates the transmitter serial and parallel clocks for the four XAUI channels. The x6 clock line carries the transmitter clocks to the PMA and PCS of each of the four channels.

Table 38.  Input Reference Clock Frequency and Interface Speed Specifications for XAUI Configurations
Input Reference Clock Frequency (MHz) FPGA Fabric-Transceiver Interface Width FPGA Fabric-Transceiver Interface Frequency (MHz)
156.25 16-bit data, 2-bit control 156.25

Transceiver Channel Placement Guidelines

In the soft PCS implementation of the XAUI configuration, all four channels must be placed continuously. The channels may all be placed in one bank or they may span two banks.

Figure 132. Transceiver Channel Placement Guidelines in a XAUI ConfigurationUse one of the two allowed channel placements when using either the CMU PLL or the ATX PLL to drive the XAUI link. The Quartus II software implements the XAUI PCS in soft logic.

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