Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 2/15/2017
Public
Document Table of Contents

4.7.3. Transceiver Channel Placement Guidelines

You can use CMU PLLs or ATX PLLs in non-bonded and bonded configurations.

Stratix V devices allow the placement of up to five channels when a CMU PLL is used or up to six channels when an ATX PLL is used in a non-bonded configuration within the same transceiver bank:

  • Custom PHY IP with standard PCS datapath configuration
  • Low Latency PHY IP with Standard PCS or 10G PCS (same data rate) in low latency datapath configuration
Figure 148. Non-Bonded Channel Placement Guidelines with Standard and 10G PCS in Custom and Low Latency Datapath ConfigurationsAll channels are assumed to contain a transmitter and receiver.


Stratix V devices allow the placement of up to four channels when a CMU PLL is used or up to six channels when an ATX PLL is used in a bonded configuration within the same transceiver bank:

  • Custom PHY IP with standard PCS datapath configuration
  • Low Latency PHY IP with Standard PCS or 10G PCS (same data rate) in low latency datapath configuration

The xN bonding method requires Logical Lane 0 be placed at either transceiver physical channel 1 or 4 within a transceiver bank. The PLL feedback compensation bonding method does not have a Logical Lane 0 assignment requirement and must be used when more than one transceiver bank is needed. However, PLL feedback compensation bonding requires the use of one PLL per transceiver bank.

Figure 149. Bonded Channel Placement Guidelines with Standard and 10G PCS in Custom and Low Latency Datapath Configurations


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